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3. Functional Description

3.

Functional Description

3.1. Block Diagram

Figure 3-1 shows the block diagram of ESP8089.

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Figure 3-1. Block Diagram

3.2. Ultra Low Power Technology

ESP8089 is designed to achieve the lowest power consumption with a combination of

several proprietary techniques. The power-saving architecture operates in two modes:

active mode and sleep mode.

With the advanced power-management techniques, ESP8089 consumes less than 12 μA

in sleep mode, and less than 1.0 mW (DTIM=3), or less than 0.5 mW (DTIM=10) to stay

connected.

In sleep mode, only the calibrated real-time clock and watchdog timer remain active. The

real-time clock can be programmed to wake up ESP8089 at any required interval.

ESP8089 can be programmed to wake up when a specified condition is detected. This

feature can be used in mobile devices, which are able to remain in low-power standby

mode until Wi-Fi functionality is needed.

3.3. Highest Level of Integration

By integrating the most important components such as power management unit, TR

switch, RF balun, high power PA capable of delivering +23 dBm (peak), ESP8089 ensures

the lowest BOM cost, and the ease of integration into any system. The only external

Analog

receive

Analog

transmit

PLL

1/2

PLL

MAC

Interface

PMU

Crystal

Bias circuits

SRAM

PMU

CPU

RF

receive

RF

transmit

VCO

Registers

Sequencers

Accelerator

GPIO

SDIO

Espressif

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2017.06