80C286SLASH883 datasheet(11/13 Pages) INTERSIL

Part #	80C286/883

Description	High Performance Microprocessor with Memory Management and Protection

PDF	13 Pages

Scroll/Zoom	100%

Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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138

80C286/883

NOTES:

1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.

2. The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC.

3. The 80C286/883 puts its status pins in a high impedance logic one state during TH.

4. For HOLD request set up to HLDA, refer to Figure 8.

5. BHE and LOCK are driven at this time but will not become valid until TS.

6. The data bus will remain in a high impedance state if a read cycle is performed.

FIGURE 5. EXITING AND ENTERING HOLD

Waveforms (Continued)

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

TH OR TI

BUS CYCLE TYPE

VCH

CLK

HILDA

VCL

(SEE NOTE 4)

12A (NOTE 3)

(SEE NOTE 3)

12B

IF TS

S1 • S0

PEACK

BHE, LOCK

A23 - A0,

M/IO,

COD/INTA

(SEE NOTE 5)

(SEE NOTE 1)

VALID

(SEE NOTE 6)

(SEE NOTE 2)

VALID IF WRITE

D15 - D0

PCLK

IF NPX TRANSFER

80C286/883 Datasheet(PDF) 11 Page - Intersil Corporation

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