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TMS320VC5503 Datasheet(PDF) 72 Page - Texas Instruments |
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TMS320VC5503 Datasheet(HTML) 72 Page - Texas Instruments |
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72 / 128 page  Electrical Specifications 72 April 2004 − Revised January 2008 SPRS245J 5.3.3 Electrical Characteristics Over Recommended Operating Case Temperature Range for CVDD = 1.6 V (200 MHz) (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage All outputs DVDD = 2.7 V−3.6 V, IOH = MAX 0.75 * DVDD V VOL Low-level output voltage SDA & SCL† At 3 mA sink current 0 0.4 V VOL Low-level output voltage All other outputs IOL = MAX 0.4 V IIZ Input current for outputs in high-impedance Output-only or I/O pins with bus keepers (enabled) DVDD = MAX, VO = VSS to DVDD −300 300 µA IIZ Input current for outputs in high-impedance All other output-only or I/O pins DVDD = MAX VO = VSS to DVDD −5 5 µA Input pins with internal pulldown (enabled) DVDD = MAX, VI = VSS to DVDD 30 300 II Input current Input pins with internal pullup (enabled) DVDD = MAX, VI = VSS to DVDD −300 −30 µA II Input current X2/CLKIN DVDD = MAX, VI = VSS to DVDD −50 50 µA All other input-only pins DVDD = MAX, VI = VSS to DVDD −5 5 IDDC CVDD supply current, CPU + internal memory access‡ CVDD = 1.6 V CPU clock = 200 MHz TC = 25_C 0.60 mA/ MHz IDDP DVDD supply current, pins active§ DVDD = 3.3 V CPU clock = 200 MHz TC = 25_C 5.5 mA IDDC CVDD supply current, standby¶ Oscillator disabled. All domains in low-power state CVDD = 1.6 V TC = 25_C (Nominal Process) 150 µA IDDP DVDD supply current, standby Oscillator disabled. All domains in low-power state. DVDD = 3.3 V No I/O activity TC = 25_C 10 µA Ci Input capacitance 3 pF Co Output capacitance 3 pF † The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. ‡ CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active. All other domains are idled. § One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load. ¶ In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time. |
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