86

To avoid introducing distortion, the source resistance

must be very low, or constant with signal level. The

output impedance provided by most op amps is ideal.

Pins 26 Digital Supply Voltage (V

Supply Voltage (V

to maximize accuracy on the chip. They should be

connected together as close as possible to the unit. Pin

27maybeslightlymoresensitivethanpin26tosupply

variations, but to maintain maximum system accu-

racy, both should be well–isolated from digital sup-

plies with wide load variations.

To limit the effects of digital switching elsewhere in a

system on the analog performance of the system, it

often makes sense to run a separate +5V supply

conductor from the supply regulator to any analog

components requiring +5V, including the SP86XX

Series. If the SP86XX Series traces cannot be

separated back to the power supply terminals, and

therefore share the same trace as the logic supply

currents, then a 10 Ohm isolating resistor should be

used between the board supply and pin 24 (V

its bypass capacitors to keep V

pins (26 and 27) should be connected together and

bypassed with a parallel combination of a 6.8

µF

Tantalum capacitor and a 0.1

µF ceramic capacitor

located close to the converter to obtain noise-free

operation. (See Figure 1). Noise on the power supply

lines can degrade converter performance, especially

noise and spikes from a switching power supply.

Appropriate supplies or filters must be used.

TheGNDpins(5and16)arealsoseparatedinternally,

and should be directly connected to a ground plane

undertheconverter.Agroundplaneisusuallythebest

solution for preserving dynamic performance and

reducing noise coupling into sensitive converter cir-

cuits. Where any compromises must be made, the

common return of the analog input signal should be

referenced to pin 5, AGND, on the SP86XX Series,

which prevents any voltage drops that might occur in

the power supply common returns from appearing in

series with the input signal.

Couplingbetweenanaloginputanddigitallinesshould

be minimized by careful layout. For instance, if the

lines must cross, they should do so at right angles.

Parallel analog and digital lines should be separated

from each other by a pattern connected to common.

If external full scale and offset potentiometers are

used, the potentiometers and related resistors should

be located as close to the SP86XX Series as possible.

“Hot Socket” Precaution

Two separate +5V V

minimize noise caused by digital transients. If one pin

is powered and the other is not, the SP86XX Series

maydrawexcessivecurrent.Innormaloperation,this

is not a problem because both pins will be soldered

together. However, during evaluation, incoming in-

spection, repair, etc., where the potential of a “Hot

Socket” exists, care should be taken to apply power to

Figure 4. Acquisition and Conversion Timing

R/C

BUSY

Converter

Mode

Acquisition

Conversion

Acquisition

Conversion

Hold Time

SYMBOL/PARAMETER

MIN.

TYP.

MAX.

UNITS

t

DBC

BUSY delay from R/C

80

150

ns

t

B

BUSY Low

2.5

2.7

µs

SP8603

4.5

4.7

µs

SP8605

9.5

9.7

µs

SP8610

t

AP

Aperture Delay

13

ns

∆t

AP

Aperture Jitter

150

ps, rms

t

C

Conversion Time

2.47

2.70

µs

SP8603

4.47

4.70

µs

SP8605

9.47

9.70

µs

SP8610