UPD360 datasheet(195/221 Pages) MICROCHIP

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DS00002084C-page 195

UPD360

14.0

DISPLAYPORT HOT PLUG DETECT (HPD)

14.1

Overview

The device provides hardware offload support for detecting the state of a Display Port compliant HPD input pin to the

device.

The USB Type-C DisplayPort Alternate Mode Specification defines the HPD state in terms of two status flags:

• HPD_STATE: Indicates whether the HPD’s logical state is high or low (denoted as HPD_HIGH or HPD_LOW,

respectively). For the purposes of communicating the HPD state over USB, the logical state of HPD is considered

as remaining high while receiving an IRQ_HPD, and is low during the time that HPD is being de-bounced on a

new mechanical connection. The logical state of HPD transitions from high to low when a low level on the HPD link

has been detected for 2ms (i.e., longer than the maximum IRQ_HPD pulse detection time). The logical state of

HPD is unchanged during glitches (as specified in DP v1.3) on the HPD link.

• IRQ_HPD: Indicates an IRQ_HPD (i.e., a high-to-low transition on HPD followed by a low-to-high transition was

detected between 250us and 2ms later, as specified in DP v1.3).

14.2

HPD Receiver

The device provides HPD detection (input) via the HPD pin. HPD detection is enabled by setting HPD Enable bit and

configuring the HPD pin to be an input via HPD Configuration in HPD Control Register (HPD_CTL). Upon setting this

bit, the device continuously monitors the state of the HPD pin as follows:

• When an IRQ_HPD event occurs, the IRQ_HPD interrupt bit in HPD Interrupt Status Register (HPD_INT_STS)

will assert. IRQ_HPD is detected when HPD is initially high and de-asserts for a time greater than or equal to the

value in the IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME) and less than or equal to the value in the

IRQ_HPD Maximum Time Register (IRQ_HPD_MAX_TIME).

• When a Low to High transition is debounced and detected, the HPD_HIGH interrupt bit in HPD Interrupt Status

time greater than or equal to the value in the HPD High Detect Time Register (HPD_HIGH_DET_TIME).

• When a High to Low transition is debounced and detected, the HPD_LOW interrupt bit in HPD Interrupt Status

greater than or equal to the value in the HPD Low Detect Time Register (HPD_LOW_DET_TIME).

APPLICATION NOTE: The HPD Interrupt Status Register (HPD_INT_STS) contents are reset to 00h when HPD

Enable is cleared.

APPLICATION NOTE: Enabled and asserted interrupts trigger the HPD_INT interrupt in the Interrupt Status Register

(INT_STS).

A mechanism has been added via the HPD Event Queue Register (HPD_QUEUE) to record up to four HPD events.

This function is enabled when HPD Enable is set and HPD Configuration indicates the HPD pin is operating as an input.

See Section 14.4.4, "HPD Event Queue Register (HPD_QUEUE)," on page 199 for additional details.

APPLICATION NOTE: The state of the HPD pin is available by reading HPD State in HPD Control Register

(HPD_CTL).

This feature is used as follows:

Software configures IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME), IRQ_HPD Maximum Time Reg-

ister (IRQ_HPD_MAX_TIME), HPD High Detect Time Register (HPD_HIGH_DET_TIME) and HPD Low Detect

Time Register (HPD_LOW_DET_TIME). To comply with the DisplayPort specification for IRQ_HPD, the

IRQ_HPD Minimum Time Register (IRQ_HPD_MIN_TIME) and IRQ_HPD Maximum Time Register (IRQ_HPD_-

MAX_TIME) should be configured to 250 us and 2 ms, respectively. Likewise, HPD Low Detect Time Register

(HPD_LOW_DET_TIME) should be configured to greater than 2 ms.

If desired, interrupts may be enabled by asserting the respective bits in the HPD Interrupt Enable Register

(HPD_INT_EN).

HPD Enable is set and HPD Configuration is cleared in the HPD Control Register (HPD_CTL).

Note:

The HPD pin is always configured as a push/pull driver.

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