UPD360 datasheet(162/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 162

 2016-2017 Microchip Technology Inc.

11.4.3.12

Reset Control Register (RESET_CTL)

Address:

1A8Bh

Size:

8 bits

Bits

Description

Type

Default

SW_RESET

Software generated PD MAC reset. Software can use this bit to reset the PD

MAC to its POR state.

Software should toggle this bit, i.e., set it and clear it. After clearing this bit,

software will have to re initialize the PD MAC, including the BMC registers.

This bit is reset by RESET_N.

R/W

BMC_SW_RESET

Software generated BMC reset. Software can use this bit to reset the BMC

encoder/decoder to its POR state.

Software should toggle this bit, i.e., set it and clear it. The BMC registers are

NOT affected by this reset.

R/W

5:1

RESERVED

PD_RESET

Software should set this bit when it is done processing a PD Hard Reset,

Cable Reset or Cable Reset so hardware can return to PD Reset state. Soft-

ware should toggle this bit, i.e., set it and clear it.

The following are reset by PD_RESET:

• RX_CTL FSM goes to POR state except Hard and Cable Reset process-

ing remains enabled if it was previously enabled by enabling the receiver.

• TX_CTL FSM goes to POR state.

• TX parallel to serial and 4b5b encoder

• TX Control Register B (TX_CTL_B) GO, TX_HARD_RESET, TX_CA-

BLE_RESET bits

• TX Parameters Register A (TX_PARAM_A) EN_FWTX bit

The following are not reset:

• All PD MAC registers, except as listed above.

• Various TX packet counters are NOT reset (NUM_PD_PACKETS_SENT,

NUM_MISSING_GCRC_MSG, NUM_MISSING_GCRC_MSG_SENT).

• Various RX packet counters are NOT reset (RX_BADCRC_PKT_CNT,

RX_DUP_PKT_CNT, NUM_PD_PACKETS_RECVD).

• RX FIFO is NOT reset.

• RX CDR, 4b5b decoder, and CRC are not reset.

• TX IFG timer and CRC are not reset.

• BIST and Power Management functions are not reset.

• BMC encoder/decoder.

R/W

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