 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
WM8742GEDS/V Datasheet(PDF) 13 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
WM8742GEDS/V Datasheet(HTML) 13 Page - Cirrus Logic |
|
|
13 / 66 page  WM8742 Rev 4.4 13 DSD AUDIO INTERFACE TIMING DSDCLK64 DSD[0:1] D[n] D[n-1] t DH D[n+1] t 64CY t 64L t 64H t DS t DC Figure 3 DSD Audio Timing - Normal Mode DSDCLK64 DSD[0:1] D[n-1] D[n] D[n] D[n+1] t64CY tDC t64L Figure 4 DSD Audio Timing - Phase Modulated Mode Test Conditions DVDD = 3.3V, GND = 0V, TA = +25 oC, fs = 44.1kHz, DSDCLK64 = 64fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information DSDCLK64 cycle time t64CY 354.3 ns DSDCLK64 pulse width high t64H 140 ns DSDCLK64 pulse width low t64L 140 ns DSD[0:1] set-up time to DSDCLK64 rising edge tDSN 20 ns DSD[0:1] hold time from DSDCLK64 rising edge tDHN 20 ns Difference in edge timing of DSD[0:1] to DSDCLK64 tDC -10 10 ns Table 3 DSD Audio Interface Timing Requirements |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
