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ROMSPG3.01 Datasheet(PDF) 13 Page - u-blox AG |
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ROMSPG3.01 Datasheet(HTML) 13 Page - u-blox AG |
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13 / 31 page ![]() CAM-M8 - Data Sheet UBX-15031574 - R04 Page 13 of 31 Production Information 1.15 Protocols and interfaces Protocol Type NMEA Input/output, ASCII, 0183, version 4.0 (Configurable to V 2.1, V 2.3 or V4.1 ) UBX Input/output, binary, u-blox proprietary RTCM Input, message 1, 2, 3, 9 Table 4: Available Protocols All protocols are available on UART, DDC (I2C compliant) and SPI. For specification of the various protocols, see the u-blox 8 / u-blox M8 Receiver Description Including Protocol Specification [2]. 1.16 Interfaces A number of interfaces are provided for data communication. The embedded firmware uses these interfaces according to their respective protocol specifications. 1.16.1 UART The CAM-M8 series modules support 1 UART interfaces, which can be used for communication to a host. It supports configurable baud rates. For supported baud rates, see the u-blox 8 / u-blox M8 Receiver Description Including Protocol Specification [2]. ☞ Designs must allow access to the UART and the SAFEBOOT_N function pin for future service, updates and reconfiguration. 1.16.2 SPI The SPI interface is designed to allow communication to a host CPU. The interface can be operated in slave mode only. The maximum transfer rate using SPI is 125 kB/s and the maximum SPI clock frequency is 5.5 MHz. ☞ SPI is not available in the default configuration, because its pins are shared with the UART and DDC interfaces. The SPI interface can be enabled by connecting D_SEL (pin 20) to ground (see section 3.1). 1.16.3 Display Data Channel (DDC) An I2C compliant DDC interface is available for communication with an external host CPU or u-blox cellular modules. The interface can be operated in slave mode only. The DDC protocol and electrical interface are fully compatible with the Fast-Mode of the I2C industry standard. Since the maximum SCL clock frequency is 400 kHz, the maximum transfer rate is 400 kb/s. ☞ The maximum bit rate is 400 kb/s. The interface stretches the clock when slowed down while serving interrupts, so real bit rates may be slightly lower. |
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