MSP430F6435IPZR datasheet(60/128 Pages) TI

60 / 128 page

9.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table

9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-3. Interrupt Sources, Flags, and Vectors of MSP430F643x Configurations

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

System Reset

Power-Up, External Reset

Watchdog Time-out, Key Violation

Flash Memory Key Violation

WDTIFG, KEYV (SYSRSTIV)(1) (3)

Reset

0FFFEh

63, highest

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG,

VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)

(1)

(Non)maskable

0FFFCh

User NMI

NMI

Oscillator Fault

Flash Memory Access Violation

NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)(1) (3)

(Non)maskable

0FFFAh

Comp_B

Comparator B interrupt flags (CBIV)(1) (2)

Maskable

0FFF8h

Timer TB0

TB0CCR0 CCIFG0(2)

Maskable

0FFF6h

Timer TB0

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)(1) (2)

Maskable

0FFF4h

Watchdog Interval Timer Mode

WDTIFG

Maskable

0FFF2h

USCI_A0 Receive or Transmit

UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)

Maskable

0FFF0h

USCI_B0 Receive or Transmit

UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)

Maskable

0FFEEh

ADC12_A

ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (2)

Maskable

0FFECh

Timer TA0

TA0CCR0 CCIFG0(2)

Maskable

0FFEAh

Timer TA0

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)(1) (2)

Maskable

0FFE8h

LDO-PWR

LDOOFFIG, LDOONIFG, LDOOVLIFG

Maskable

0FFE6h

DMA

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG,

DMA5IFG (DMAIV)(1) (2)

Maskable

0FFE4h

Timer TA1

TA1CCR0 CCIFG0(2)

Maskable

0FFE2h

Timer TA1

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)(1) (2)

Maskable

0FFE0h

I/O Port P1

P1IFG.0 to P1IFG.7 (P1IV)(1) (2)

Maskable

0FFDEh

USCI_A1 Receive or Transmit

UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)

Maskable

0FFDCh

USCI_B1 Receive or Transmit

UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)

Maskable

0FFDAh

I/O Port P2

P2IFG.0 to P2IFG.7 (P2IV)(1) (2)

Maskable

0FFD8h

LCD_B

LCD_B Interrupt Flags (LCDBIV)(1)

Maskable

0FFD6h

RTC_B

RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,

RT1PSIFG, RTCOFIFG (RTCIV)(1) (2)

Maskable

0FFD4h

DAC12_A(5)

DAC12_0IFG, DAC12_1IFG(1) (2)

Maskable

0FFD2h

Timer TA2

TA2CCR0 CCIFG0(2)

Maskable

0FFD0h

Timer TA2

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)(1) (2)

Maskable

0FFCEh

I/O Port P3

P3IFG.0 to P3IFG.7 (P3IV)(1) (2)

Maskable

0FFCCh

I/O Port P4

P4IFG.0 to P4IFG.7 (P4IV)(1) (2)

Maskable

0FFCAh

Reserved

Reserved(4)

0FFC8h

⋮

0FF80h

0, lowest

(1)

Multiple source flags

(2)

Interrupt flags are in the module.

(3)

A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4)

Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To

maintain compatibility with other devices, TI recommends reserving these locations.

MSP430F6438, MSP430F6436, MSP430F6435, MSP430F6433

SLAS720F – AUGUST 2010 – REVISED SEPTEMBER 2020

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