MSP430F6637IPZ datasheet(21/133 Pages) TI

21 / 133 page

8.3 Recommended Operating Conditions (continued)

MIN

NOM

MAX UNIT

CDVCC/

CVCORE

Capacitor ratio of DVCC to VCORE

fSYSTEM

Processor frequency (maximum MCLK frequency)(3) (5)

(see Figure 8-1)

PMMCOREVx = 0,

1.8 V ≤ VCC ≤ 3.6 V

(default condition)

8.0

MHz

PMMCOREVx = 1,

2 V ≤ VCC ≤ 3.6 V

12.0

PMMCOREVx = 2,

2.2 V ≤ VCC ≤ 3.6 V

16.0

PMMCOREVx = 3,

2.4 V ≤ VCC ≤ 3.6 V

20.0

fSYSTEM_USB

Minimum processor frequency for USB operation

1.5

MHz

USB_wait

Wait state cycles during USB operation

cycles

(1)

TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2)

The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 8.23

for the exact values and more details.

(3)

The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(4)

A capacitor tolerance of ±20% or better is required.

(5)

Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(6)

USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.

2.0

1.8

Supply Voltage - V

NOTE: The numbers within the fields denote the supported PMMCOREVx settings.

2.2

2.4

3.6

0, 1, 2, 3

0, 1, 2

0, 1

1, 2, 3

1, 2

2, 3

Figure 8-1. Frequency vs Supply Voltage

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SLAS566G – JUNE 2010 – REVISED SEPTEMBER 2020

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