MCP6V76 datasheet(17/48 Pages) MICROCHIP

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DS20006323B-page 17

MCP6V76/6U/7/9

4.0

APPLICATIONS

The MCP6V76/6U/7/9 family of zero-drift op amps is

manufactured using Microchip’s state of the art CMOS

process. It is designed for applications with require-

ments for small packages and low power. Its low supply

voltage and low quiescent current make the

MCP6V76/6U/7/9 devices ideal for battery-powered

applications.

4.1

Overview of Zero-Drift Operation

Figure 4-1 shows a simplified diagram of the

MCP6V76/6U/7/9 zero-drift op amp. This diagram will

be used to explain how slow voltage errors are reduced

in this architecture (much better VOS, ∆VOS/∆TA (TC1),

CMRR, PSRR, AOL and 1/f noise).

FIGURE 4-1:

Simplified Zero-Drift Op

Amp Functional Diagram.

4.1.1

BUILDING BLOCKS

The Main amplifier is designed for high gain and

bandwidth, with a differential topology. Its main input

pair (+ and - pins at the top left) is used for the higher

frequency portion of the input signal. Its auxiliary input

pair (+ and - pins at the bottom left) is used for the low-

frequency portion of the input signal and corrects the

op amp’s input offset voltage. Both inputs are added

together internally.

The Auxiliary amplifier, chopper input switches and

chopper output switches provide a high DC gain to the

input signal. DC errors are modulated to higher

frequencies, while white noise is modulated to low

frequencies.

The low-pass filter reduces high-frequency content,

including harmonics of the chopping clock.

The output buffer drives external loads at the VOUT pin

(VREF is an internal reference voltage).

The oscillator runs at fOSC1 = 200 kHz. Its output is

divided by two to produce the chopping clock rate of

fCHOP = 100 kHz.

The internal POR part starts the part in a known good

state, protecting against power supply brown-outs.

The digital control block controls switching and POR

events.

4.1.2

CHOPPING ACTION

Figure 4-2 shows the amplifier connections for the first

phase of the chopping clock and Figure 4-3 shows

them for the second phase. Its slow voltage errors

alternate in polarity, making the average error small.

FIGURE 4-2:

First Chopping Clock Phase;

Equivalent Amplifier Diagram.

FIGURE 4-3:

Second Chopping Clock

Phase; Equivalent Amplifier Diagram.

VIN+

VIN–

Main

Buffer

VOUT

VREF

Amp.

Output

Aux.

Amp.

Chopper

Input

Switches

Chopper

Output

Switches

Oscillator

Low-Pass

Filter

POR

Digital Control

VIN+

VIN–

Main

Amp.

Aux.

Amp.

Low-Pass

Filter

VIN+

VIN–

Main

Amp.

Aux.

Amp.

Low-Pass

Filter

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