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DF69 Datasheet(PDF) 45 Page - PADAUK Technology.

Part # DF69
Description  DC Fan Controller
PDF  106 Pages
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Manufacturer  PADAUK [PADAUK Technology.]
Direct Link  http://www.padauk.com.tw/
Logo PADAUK - PADAUK Technology.

DF69 Datasheet(HTML) 45 Page - PADAUK Technology.

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DF69
DC Fan Controller
5-12-3. Wake-up
After entering the Power-Down or Power-Save modes, the DF69 can be resumed to normal operation by
toggling IO pins, Timer16 interrupt is available for Power-Save mode ONLY. Fig. 5-12-2 shows the
differences in wake-up sources between STOPSYS and STOPEXE.
Differences in wake-up sources between STOPSYS and STOPEXE
IO Toggle
T16 Interrupt
STOPSYS
Yes
No
STOPEXE
Yes
Yes
Fig. 5-12-2 Differences in wake-up sources between Power-Save mode and Power-Down mode
When using the IO pins to wake-up the DF69, registers padier and pbdier should be properly set to enable
the wake-up function for every corresponding pin. The wake-up time for normal wake-up is about 1024
ILRC clocks counting from wake-up event; fast wake-up can be selected to reduce the wake-up time by
misc register. For fast wake-up mechanism, the wake-up time is 128 system clocks from IO toggling if
STOPEXE was issued, and 128 system clocks plus oscillator (IHRC or ILRC) stable time from IO toggling if
STOPSYS was issued. The oscillator stable time is the time for IHRC or ILRC oscillator from power-on,
depending on which oscillator is used as system clock source. Please notice that there is no fast wake-up
mode whenever EOSC is enabled.
Suspend
mode
wake-up
mode
system clock
source
wake-up time (tWUP) from IO toggle
STOPEXE
suspend
fast wake-up
IHRC or ILRC
128 * TSYS,
Where TSYS is the time period of system clock
STOPSYS
suspend
fast wake-up
IHRC
128 TSYS + TSIHRC;
Where TSIHRC is the stable time of IHRC from
power-on.
STOPSYS
suspend
fast wake-up
ILRC
128 TSYS + TSILRC;
Where TSILRC is the stable time of ILRC from
power-on.
STOPSYS or
STOPEXE
suspend
fast wake-up
EOSC
1024 * TILRC,
Where TILRC is the clock period of ILRC
STOPEXE
suspend
normal
wake-up
Any one
1024 * TILRC,
Where TILRC is the clock period of ILRC
STOPSYS
suspend
normal
wake-up
Any one
1024 * TILRC,
Where TILRC is the clock period of ILRC
©Copyright 2018, PADAUK Technology Co. Ltd
Page 45 of 106
PDK-DS-DF69_V003 – Apr. 18, 2018



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