AD2428W datasheet(4/38 Pages) AD

4 / 38 page

Rev. B

Page 4 of 38

January 2020

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

A2B BUS DETAILS

Figure 2 shows a single-master, multiple-slave A2B communica-

tions system with the master transceiver controlled by the host.

The host generates a periodic synchronization signal on the

I2S/TDM interface at a fixed frequency (typically 48 kHz) to

which all A2B nodes synchronize.

Communications along the A2B bus occur in periodic super-

frames. The superframe frequency is the same as the

synchronization signal frequency, and data is transferred at a bit

rate that is 1024 times faster (typically 49.152 MHz). Each

superframe is divided into periods of downstream transmission,

upstream transmission, and no transmission (where the bus is

not driven). Data is exchanged over the A2B bus in up to 32

equal width slots for both upstream and downstream

transmissions.

The A2B bus also communicates the following control and

status information between nodes:

•I2C to I2C communication

• General-purpose input/output (GPIO)

•Interrupts

In Figure 3, a superframe is shown with an initial period of

downstream transmission and a later period of upstream

transmission.

All signals on the A2B bus are line coded, and the master node

forwards the synchronization signal downstream from the mas-

ter transceiver to the last slave node transceiver in the form of a

synchronization preamble. This preamble is followed by control

data to build a synchronization control frame (SCF). Down-

stream, TDM synchronous data is added directly after the

control frame. Every slave can use or consume some of the

downstream data and add data for downstream nodes. The last

slave node transceiver responds after the response time with a

synchronization response frame (SRF). Upstream synchronous

data is added by each node directly after the response frame.

Each node can also use or consume upstream data.

The embedded control and response frames allow the host to

individually address each slave transceiver in the system. The

host also enables access to remote peripheral devices that are

connected to the slave transceivers via the I2C or SPI ports for

I2C to I2C communication over distance between multiple

nodes.

All nodes in an A2B system are sampled synchronously in the

same A2B superframe. Synchronous I2S/TDM downstream data

from the master arrives at all slaves in the same A2B superframe,

and the upstream audio data of every node arrives synchro-

nously in the same I2S/TDM frame at the master. The remaining

audio phase differences between slaves can be compensated for

by register-programmable fine adjustment of the SYNC pin sig-

nal delay.

There is a sample delay incurred for data moving between the

A2B bus and the I2S/TDM interfaces because data is received

and transmitted over the I2S/TDM every sample period (typi-

cally 48 kHz). This timing relationship between samples over

the A2B bus is shown in Figure 4.

Note in Figure 4, both downstream and upstream samples are

named for the frame where they enter the A2B system as follows:

• Data transmitted by the master node transceiver in Super-

frame M creates Downstream Data M.

• Data transmitted by the slave node transceivers in Super-

frame N creates Upstream Data N.

• Data received over the I2S/TDM interface by the A2B trans-

ceiver is transmitted over the A2B bus in the next

superframe.

•Data on the A2B bus is transmitted over the I2S/TDM inter-

face of an A2B transceiver in the next superframe.

• Data transmitted across the A2B bus (master to slave or

slave to master) has two frames of latency plus any internal

delay that has accumulated in the transceivers as well as

delays due to wire length. Therefore, overall latency is

slightly over two samples (<50 μs at 48 kHz sample periods)

from the I2S/TDM interface in one A2B transceiver to the

I2S/TDM interface of another A2B transceiver.

To support and extend the A2B bus functions and performance,

the transceivers have additional features, as described in the fol-

lowing sections.

Figure 2. Communication System Block Diagram

HOST

DSP

I2C

MASTER

A2B

TRANSCEIVER

SLAVE A2B

TRANSCEIVER

I2S/TDM

SLAVE A2B

TRANSCEIVER

SLAVE A2B

TRANSCEIVER

I2S/TDM

I2C

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