AD2428W datasheet(24/38 Pages) AD

24 / 38 page

Rev. B

Page 24 of 38

January 2020

AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W)

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

The 32-lead LFCSP_SS package pin configuration is shown in

Figure 33. The pin function descriptions are shown in Table 15.

All digital inputs and digital outputs are three-stated with inputs

disabled during reset.

Figure 33. 32-Lead LFCSP_SS and LFCSP Package Pin Configuration

Table 15. AD2420(W)/AD2426(W)/AD2427(W)/AD2428(W)/AD2429(W) Pin Function Descriptions



No.

Pin Name

Type

Alternate



Functions

Description

PLLVDD

PWR

None

Power Supply for PLL. PLLVDD can be supplied by VVOUT1.

2, 3

DVDD

PWR

None

Power Supply for Digital Core Logic. DVDD can be supplied by VVOUT1.

SCL

D_IO

None

Serial Clock for I

2C Data Transfers. Digital input in A2B master mode. Digital input (I2C slave) or

output (I

2C master) in A2B slave mode. This pin uses open-drain I/O cells and must be pulled up

to VI2C_VBUS through a resistor (consult Version 2.1 of the I

2C bus specification for the proper

resistor value). Connect the pin to ground when the I

2C interface is not used.

SDA

D_IO

None

I2C Mode Serial Data. This pin is a bidirectional open-drain input/output and must be pulled up

to VI2C_VBUS through a resistor (consult Version 2.1 of the I

2C bus specification for the proper

resistor value). Connect the pin to ground if the I2C interface is not used.

IRQ/IO0

D_IO

None

Interrupt Request Output. In master mode, A

2B transceivers create event driven interrupt

requests towards the host controller.

In slave mode, this pin indicates mailbox empty/full status to the slave node processor when

mailbox interrupts are enabled.

When not serving as an interrupt output pin, this pin serves as a general-purpose I/O pin with

interrupt request input capability. The IRQ/IO0 pin must be initialized to become either an input

or an output. This pin is high impedance by default.

ADR1/IO1

D_IO

CLKOUT1

The ADR1/IO1 and ADR2/IO2 pins set the I2C slave device address during power-on reset; up to

four A2B master transceiver chips connect to the same I2C bus. The ADR1/IO1 pin is high

impedance by default. The ADR1/IO1 pin can then be initialized to become a general-purpose

input/output (GPIO) pin with interrupt request capability.

This pin can be programmed to become a clock output (CLKOUT1). The clock output can be used

as a master clock for connected ADCs and DACs or to synchronize switching voltage regulators.

In this table, the Type is defined as follows: PWR = power/ground, A_IN = analog input, D_OUT = digital output, A_IO = analog input/output,

D_IO = digital input/output, N/A = not applicable.

9 10 11 121314 1516

32 31 30 29 28 27 26 25

PLLVDD

DVDD

SCL

SDA

IRQ/IO0

ADR1/IO1

ADR2/IO2

BCM

BTRXVDD

ATRXVDD

ACM

EPAD

(PIN 33)

TOP VIEW

PIN 33 IS THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. THIS PIN MUST BE CONNECTED TO GND.

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