NCP5331 datasheet(9/38 Pages) ONSEMI

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NCP5331

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PACKAGE PIN DESCRIPTION

Pin No.

Symbol

Description

VFB

Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP), set the light load offset voltage

by connecting a resistor between VFB and VCORE. The resistor and the VFB bias current determine

the offset. For no adaptive positioning connect VFB directly to VCORE.

VDRP

Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC

voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the

amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 4.1 Vdc.

LGND

Return for the internal control circuits and the IC substrate connection.

4, 6

CS1, CS2

Current sense inputs. Connect the current sense network for the corresponding phase to each in-

put. The input voltages to these pins must be kept within 125 mV of CSREF.

CSREF

Reference for both differential current sense amplifiers. To balance input offset voltages between

the inverting and non-inverting inputs of the Current Sense Amplifiers, connect this pin to the output

voltage through a resistor equal to one third of the value of the current sense resistors.

VFFB

Fast Feedback connection to the PWM comparators and input to the Power Good comparator.

5 VREF

Reference output. Decouple to LGND with 0.1

µF.

ROSC

A resistor from this pin to ground sets the operating frequency and VFB bias current.

-SEN

Ground connection for the DAC. Provides remote sensing of ground at the load.

11-15

VID pins

Voltage ID DAC inputs. These pins are internally pulled up and clamped at 2.3 V if left unconnected.

VCCL2

Power for GL2.

GL2

Low side driver #2.

GND2

Return for driver #2.

GH2

High side driver #2.

VCCH

Power for GH1 and GH2.

CBOUT

Open-collector crowbar output pin. This pin is high impedance when an overvoltage condition is

detected at CSREF. Connect this pin to the gate of a MOSFET or SCR to crowbar either VCORE or

VIN to GND. To prevent failure of the crowbar device, this pin should be used in conjunction with

logic on the motherboard to disable the ATX supply via PSON and/or a relatively fast fuse should be

placed upstream to disconnect the input voltage.

GH1

High side driver #1.

GND1

Return for driver #1.

GL1

Low side driver #1.

VCCL1

Power for GL1.

VCCL

Power for the internal control circuits. UVLO sense for Logic connects to this pin.

COVC

A capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit.

This timer is started by the first overcurrent condition (set by the ILIM voltage). Once timed out, volt-

age at the VCCL pin must be cycled to reset this fault. Connecting this pin to LGND ±200 mV will

disable this function and hiccup mode current limit will operate indefinitely.

CPGD

A capacitor from this pin to ground sets the programmable time between when VCORE crosses the

PWRGD threshold and when the open-collector PWRGD pin transitions from a logic Low to a logic

High. The minimum delay is internally set to 200

µs. Connecting this pin to 5 VREF will disable the

programmable timer and the delay will be set to the internal delay.

PGD

Power Good output. Open collector output that will transition Low when CSREF (VCORE) is out of

regulation.

5 VSB

Input power for the CBOUT circuitry. To provide maximum overvoltage protection to the CPU, this pin

should be connected to 5 VSB from the ATX supply (ATX, pin 9). If the CBOUT function is not used,

this pin must be connected to the NCP5331 controller’s internal voltage reference (5 VREF, pin 8).

ILIM

Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maxi-

mum working voltage is 3.0 Vdc.

COMP

Output of the error amplifier and input for the PWM comparators.

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