AD4115 datasheet(32/51 Pages) AD

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AD4115

Data Sheet

Rev. 0 | Page 32 of 51

DIGITAL INTERFACE

The programmable functions of the AD4115 are accessible via

the SPI. The serial interface consists of four signals: CS, DIN,

SCLK, and DOUT/RDY. The DIN line transfers data into the

on-chip registers. The DOUT output accesses data from the on-

chip registers. SCLK is the serial clock input for the device. All

data transfers (either on DIN or on DOUT) occur with respect to

the SCLK signal.

The DOUT/RDY pin also functions as a data ready signal

where the line goes low if CS is low when a new data-word is

available in the data register. The pin resets high when a read

operation from the data register is complete. The RDY output

also goes high before updating the data register to indicate

when not to read from the device to ensure that a data read is not

attempted while the register is updated. Take care to avoid

reading from the data register when the RDY signal is about to

go low. To ensure that no data read occurs, always monitor the

RDY output. Start reading the data register as soon as RDY

goes low and ensure a sufficient SCLK rate such that the read is

completed before the next conversion result. CS is used to select a

device and can be used to decode the AD4115 in systems where

several components are connected to the serial bus.

The timing diagrams in Figure 2 and Figure 3 show interfacing

to the AD4115 using CS to decode the device. Figure 2 shows

the timing for a read operation from the AD4115, and Figure 3

shows the timing for a write operation to the AD4115. The user

can read from the data register several times even though the RDY

output returns high after the first read operation. Ensure that

the read operations are complete before the next output update

occurs. In continuous read mode, the data register can be read

only once.

To operate the serial interface in 3-wire mode, tie CS low. In

this case, the SCLK, DIN, and DOUT/RDY lines are used to

communicate with the AD4115. The end of the conversion can

also be monitored using the RDY bit in the status register.

To reset the serial interface, write 64 serial clocks with CS = 0

and DIN = 1. A reset returns the interface to the state in which the

interface expects a write to the communications register. This

operation resets the contents of all registers to the power-on values.

Following a reset, wait 500 µs before addressing the serial interface.

CHECKSUM PROTECTION

The AD4115 has a checksum mode that can be used to improve

interface robustness. Use the checksum to ensure that only valid

data is written to a register and to allow the data read from a

write, the CRC_ERROR bit is set in the status register. To

ensure that the register write is complete, read back the register

and verify the checksum.

For CRC checksum calculations during a write operation, the

following polynomial is always used:

x8 + x2 + x + 1

During read operations, the user can select between this

polynomial and a similar exclusive OR (XOR) function. The

XOR function requires less time to process on the host

microcontroller than the polynomial-based checksum. The

CRC_EN bits in the interface mode register enable and disable

the checksum and allow the user to select between the

polynomial checksum and the simple XOR checksum.

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8-bit to

24-bit data. For a read transaction, the checksum is calculated

using the command word and the 8-bit to 32-bit data output.

Figure 21 and Figure 22 show SPI write and read transactions,

respectively.

If checksum protection is enabled when continuous read mode

is active, an implied read data command of 0x44 occurs before

each data transmission, which must be accounted for when

calculating the checksum value. The checksum protection ensures

a nonzero checksum value even if the ADC data equals 0x000000.

AD4115 Datasheet(PDF) 32 Page - Analog Devices

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