AD4115 datasheet(29/51 Pages) AD

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Data Sheet

AD4115

Rev. 0 | Page 29 of 51

OPERATING MODES

The AD4115 has nine operating modes that can be set from the

ADC mode register and interface mode register (see Table 22

and Table 23). These modes include the following:

•

Continuous conversion mode

•

Continuous read mode

•

Single conversion mode

•

Standby mode

•

Power-down mode

•

Four calibration modes

CONTINUOUS CONVERSION MODE

Continuous conversion mode (see Figure 42) is the default

power-up mode. The AD4115 converts continuously, and the

RDY bit in the status register goes low each time a conversion is

complete. If CS is low, the RDY output also goes low when a

conversion is complete. To read a conversion, write to the

communications register to indicate that the next operation is a

read of the data register. When the data-word is read from the

data register, the DOUT/RDY pin goes high. The user can read

this register additional times, if required. However, ensure that

the data register is not accessed at the completion of the next

conversion. Otherwise, the new conversion word is lost.

When several channels are enabled, the ADC automatically

sequences through the enabled channels and performs one

conversion on each channel. When all channels are converted,

the sequence starts again with the first channel. The channels

are converted in order from the lowest enabled channel to the

highest enabled channel. The data register updates as soon as

each conversion is available. The RDY output pulses low each

time a conversion is available and the user can then read the

conversion while the ADC converts the next enabled channel.

If the DATA_STAT bit in the interface mode register is set to 1,

the conversion data and the contents of the status register are

output each time the data register is read. The four LSBs of the

status register indicate the channel to which the conversion

corresponds.

CONTINUOUS READ MODE

In continuous read mode (see Figure 43), it is not required to

write to the communications register before reading ADC data.

Apply only the required number of serial clocks after the RDY

output goes low to indicate the end of a conversion. When the

conversion is read, the RDY output returns high until the next

conversion is available. In this mode, the data can be read only

once. Ensure that the data-word is read before the next

conversion is complete. If the user has not read the conversion

before the completion of the next conversion, or if insufficient

serial clocks are applied to the AD4115 to read the data-word,

the serial output register resets shortly before the next

conversion is complete, and the new conversion is placed in the

output serial register. The ADC must be configured for

continuous conversion mode to use continuous read mode. To

enable continuous read mode, set the CONTREAD bit in the

interface mode register. When this bit is set, the only serial

interface operations possible are reads from the data register. To

exit continuous read mode, issue a dummy read of the ADC data

Alternatively, apply a software reset (64 serial clocks with CS = 0

and DIN = 1) to reset the ADC and all register contents. The

dummy read and the software reset are the only commands that

the interface recognizes after the interface is placed in

continuous read mode. Hold DIN low in continuous read mode

until an instruction is to be written to the device.

If multiple ADC channels are enabled, each channel is output

in turn with the status bits appended to the data if the

DATA_STAT bit is set in the interface mode register. The four

LSBs of the status register indicate the channel to which the

conversion corresponds.

SINGLE CONVERSION MODE

In single conversion mode (see Figure 44), the AD4115

performs a single conversion and is placed in standby mode

when the conversion is complete. The RDY output goes low to

indicate the completion of a conversion. When the data-word is

read from the data register, the RDY output goes high. The data

RDY output goes high.

If several channels are enabled, the ADC automatically

sequences through the enabled channels and performs a

conversion on each channel. When the first conversion starts,

the RDY output goes high and remains high until a valid

conversion is available and CS is low. When the conversion is

available, the RDY output goes low and the ADC selects the

next channel and begins a conversion. The user can read the

present conversion while the next conversion is performed.

When the next conversion is complete, the data register

updates, which allows the user a limited period in which to read

the conversion. When the ADC performs a single conversion

on each selected channel, the ADC returns to standby mode.

If the DATA_STAT bit in the interface mode register is set to 1,

the contents of the status register and the conversion are output

each time the data register is read. The four LSBs of the status

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