Density Octal SPST Switch

Data Sheet

ADGS1414D

Rev. 0

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FEATURES

SPI with error detection

Includes CRC, invalid read and write address, and SCLK

count error detection

Supports burst mode and daisy-chain mode

Industry-standard SPI Mode 0 and Mode 3 interface

compatible

Integrated passive components

Route through of digital signals and supplies

Guaranteed break-before-make switching allowing external

wiring of switches to deliver multiplexer configurations

1.5 Ω typical on resistance at 25°C (±15 V dual supply)

0.3 Ω typical on resistance flatness at 25°C (±15 V dual supply)

0.1 Ω typical on resistance match between channels at 25°C

(±15 V dual supply)

Fully specified at ±15 V, ±5 V, and +12 V

readback to a 1.8 V device)

4 mm × 5 mm, 30-terminal LGA

APPLICATIONS

Automated test equipment

Data acquisition systems

Sample-and-hold systems

Audio and video signal routing

Communications systems

Relay replacement

GENERAL DESCRIPTION

The ADGS1414D contains eight independent SPST switches. A

serial peripheral interface (SPI) controls the switches. The SPI

has robust error detection features, such as cyclic redundancy

check (CRC) error detection, invalid read and write address

detection, and SCLK count error detection.

It is possible to daisy-chain multiple ADGS1414D devices

together. Daisy-chain mode enables the configuration of

multiple devices with a minimal amount of digital lines. The

route of digital signals and supplies through the ADGS1414D

allows for a further increase in channel density. Integrated

passive components eliminate the need for external passive

components.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

The ADGS1414D is suited to high density switching

applications, such as large switching matrices and fanout

applications.

Each switch conducts equally well in both directions when on,

and each switch has an input signal range that extends to the

supplies. In the off condition, signal levels up to the supplies

are blocked.

Multifunction pin names may be referenced by their relevant

function only.

PRODUCT HIGHLIGHTS

1. The SPI removes the need for parallel conversion and logic

traces and reduces the general-purpose input and output

(GPIO) channel count.

2. Daisy-chain mode removes additional logic traces when

multiple devices are used.

3. Route through of digital signals and supplies eases routing

and allows for an increase in channel density.

4. Integrated passive components eliminate the need for

external passive components.

5. CRC error detection, invalid read and write address

detection, and SCLK count error detection ensure a robust

digital interface.

6. CRC, invalid read and write address, and SCLK error

detection capabilities allow for the use of the ADGS1414D

in safety critical systems.

7. Minimum distortion.

ADGS1414D

S5

S4

S3

S1

D5

S6

D6

S7

D7

S8

D8

SDO

SCLK SDI

CS

D4

D3

D1

S2

D2

SPI

INTERFACE