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ADSP-21486KSWZ-2AB Datasheet(PDF) 24 Page - Analog Devices |
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ADSP-21486KSWZ-2AB Datasheet(HTML) 24 Page - Analog Devices |
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24 / 71 page  Rev. H | Page 24 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Clock Input Figure 4. Power-Up Sequencing Table 19. Clock Input Parameter 266 MHz 300 MHz 350 MHz 400 MHz 450 MHz Unit Min Max Min Max Min Max Min Max Min Max Timing Requirements tCK CLKIN Period 301 1 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL. 1002 2 Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL. 26.661 1002 22.81 1002 201 1002 17.751 1002 ns tCKL CLKIN Width Low 1545 134511 45 10 45 8.875 45 ns tCKH CLKIN Width High 15 45 13 45 11 45 10 45 8.875 45 ns tCKRF 3 3 Guaranteed by simulation but not tested on silicon. CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 3 3 ns tCCLK 4 4 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t CCLK. CCLK Period 3.75 10 3.33 10 2.85 10 2.5 10 2.22 10 ns fVCO 5 5 See Figure 3 on Page 22 for VCO diagram. VCO Frequency 200 800 200 800 200 800 200 800 200 900 MHz tCKJ 6, 7 6 Actual input jitter should be combined with ac specifications for accurate timing analysis. 7 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 –250 +250 –250 +250 ps Figure 5. Clock Input tRSTVDD tCLKVDD tCLKRST tCORERST tPLLRST VDDEXT VDDINT CLKIN CLK_CFG1–0 RESET RESETOUT tIVDDEVDD CLKIN tCK tCKL tCKH tCKJ |
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