ADSP-21486KSWZ-2AB datasheet(55/71 Pages) AD

55 / 71 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. H

Page 55 of 71

February 2020

OUTPUT DRIVE CURRENTS

Figure 40 shows typical I-V characteristics for the output driv-

ers of the ADSP-2148x, and Table 54 shows the pins associated

with each driver. The curves represent the current drive capabil-

ity of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 20 on Page 26 through Table 53 on Page 54. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 41.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 42. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 41). Figure 45 and Figure 46 show

graphically how output delays and holds vary with load capaci-

tance. The graphs of Figure 43 through Figure 46 may not be

linear outside the ranges shown for Typical Output Delay vs.

Load Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

Table 54. Driver Types

Driver Type Associated Pins

FLAG[0–3], AMI_ADDR[0–23], DATA[0–15],

AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,

SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU, TDO,

RESETOUT, DPI[1–14], DAI[1–20], WDTRSTO,

MLBDAT, MLBSIG, MLBSO, MLBDO, MLBCLK

BSDCLK

Figure 40. Typical Drive at Junction Temperature

Figure 42. Voltage Reference Levels for AC Measurements

SWEEP (V

DDEXT) VOLTAGE (V)

3.5

0.5

1.0

1.5

2.0

2.5

3.0

100

200

150

-100

-200

-150

-50

OH 3.13 V, 125 °C

OL 3.13 V, 125 °C

TYPE A

TYPE B

INPUT

OUTPUT

1.5V

Figure 41. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 43. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Max)

ZO = 50

(impedance)

TD = 4.04

r 1.18 ns

2pF

TESTER PIN ELECTRONICS

0.5pF

400

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

LOAD CAPACITANCE (pF)

125

200

100

175

150

y = 0.0341x + 0.3093

y = 0.0153x + 0.2131

y = 0.0414x + 0.2661

y = 0.0152x + 0.1882

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE FALL

TYPE B DRIVE RISE

ADSP-21486KSWZ-2AB Datasheet(PDF) 55 Page - Analog Devices

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