MAS3507D datasheet(13/60 Pages) MICRONAS

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PRELIMINARY DATA SHEET

MAS 3507D

Micronas

2.7.3.3. DMA Handshake Protocol

The data transfer can be started after the EOD pin of

the MAS 3507D is set to “high”. After verifying this, the

controller signalizes the sending of data by activating

the PR line. The MAS 3507D responds by setting the

RTR line to the “low” level. The MAS 3507D reads the

data PI[19:12] tpd ns after rising edge of the PR. The

next data word write operation will again be initialized

by setting the PR line via the controller. Please refer to

Figure 2–5 and Table 2–6 for the exact timing

2.7.3.4. End of DMA Transfer

The above procedure will be repeated until the

MAS 3507D sets the EOD signal to “0”, which indi-

cates that the transfer of one data block has been exe-

cuted. Subsequently, the controller should set PR to

“0”, wait until EOD rises again, and then repeat the

procedure (see Section 2.7.3.3. ) to send the next

block of data. The DMA buffer is 15 bytes long.

The recommended PIO-DMA conditions and the char-

acteristics of the PIO timing are given in Table 2–6

2.7.4. Audio Output Interface (SDO)

The audio output interface of the MAS 3507D is a

standard I2S interface. It is possible to choose between

two standard interfaces (16 bit with delay or 32 bit with-

out delay and inverted SOI) via start-up configuration.

These setup modes meet the performance of the most

common DACs. It is also possible to select other inter-

face modes via I2C commands (see Section 2.7.4.3.).

2.7.4.1. Mode 1: 16 Bits/Sample

(I2S Compatible Data Format)

A schematic timing diagram of the SDO interface in

16 bit/sample mode is shown in Fig. 2–6.

Fig. 2–6: Schematic timing of the SDO interface in 16 bit/sample mode

Table 2–6: PIO DMA Timing

Symbol

PIO Pin

Min.

Max.

Unit

tst

PR, EOD

0.010

2000

µs

PR, RTR

160

tpd

PR,

PI[19:12]

120

480

tset

PI[19:12]

160

no limit

PI[19:12]

160

no limit

trtrq

RTR

200

30000

tpr

120

no limit

trpr

PR, RTR

no limit

teod

PR, EOD

160

teodq

EOD

0500

µs

SOC

SOD

SOI

left 16-bit audio sample

right 16-bit audio sample

15 14 13 12 11 10 98

76543210

13 12 11 10

9 8

6543210

15 14

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