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DRV8300DI Datasheet(PDF) 13 Page - Texas Instruments

Part # DRV8300DI
Description  DRV8300: Three-Phase BLDC Gate Driver
PDF  27 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DRV8300DI Datasheet(HTML) 13 Page - Texas Instruments

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8.3 Feature Description
8.3.1 Three BLDC Gate Drivers
The DRV8300 integrates three half-bridge gate drivers, each capable of driving high-side and low-side N-
channel power MOSFETs. Input on GVDD provides the gate bias voltage for the low-side MOSFETs. The high
voltage is generated using bootstrap capacitor and GVDD supply. DRV8300 device integrates the bootstrap
diode. The half-bridge gate drivers can be used in combination to drive a three-phase motor or separately to
drive other types of loads.
8.3.1.1 Gate Drive Timings
8.3.1.1.1 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has two parts consisting of the input deglitcher delay and the delay through the analog gate
drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. The analog gate drivers have a small delay that contributes to the overall propagation delay of the
device.
8.3.1.1.2 Deadtime and Cross-Conduction Prevention
In the DRV8300, high- and low-side inputs operate independently, with an exception to prevent cross conduction
when high and low side are turned ON at same time. The DRV8300 turns OFF high- and low- side output to
prevent shoot through when high- and low-side inputs are logic high at same time.
The DRV8300 also provides deadtime insertion to prevents both external MOSFETs of each power-stage from
switching on at the same time. In devices with DT pin (QFN package device), deadtime can be linearily adjusted
between 200 nS to 2000 nS by connecting resistor between DT and ground. When DT pin left floating, fixed
deadtime of 200 nS (Typical value) is inserted. The value of resistor can be caculated using following equation.
4
&6
(GÀ) =
&A=@PEIA
(J5)
5
In device without DT pin (TSSOP package device), fixed deadtime of 200 nS (Typical value) is inserted to
prevent high and low side gate output turning on at same time.
INHx
INLx
GHx
GLx
INHx/INLx Inputs
GHx/GLx outputs
DT
DT
Cross
Conduction
Prevention
Figure 8-3. Cross Conduction Prevention and Deadtime Insertion
www.ti.com
DRV8300
SLVSFG5 – SEPTEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: DRV8300



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