11 Layout

11.1 Layout Guidelines

• Low ESR/ESL capacitors must be connected close to the device between GVDD and VSS pins and between

BSTx and SHx pins to support high peak currents drawn from GVDD and BSTx pins during the turn-on of the

external MOSFETs.

• To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a

good quality ceramic capacitor must be connected between the high side MOSFET drain and ground.

• In order to avoid large negative transients on the switch node (SHx) pin, the parasitic inductances between

the source of the high-side MOSFET and the source of the low-side MOSFET must be minimized.

• In order to avoid unexpected transients, the parasitic inductance of the GHx, SHx, and GLx connections must

be minimized. Minimize the length and number of vias wherever possible. Minimum10 mil trace is

recommended.

• Traces for GHx and SHx must be routed in parallel

• Resistance between DT and GND must be place close to device

11.2 Layout Example

GVDD Cap close

to device

DT resistance

close to device

BSTx and SHx

cap close to

device

www.ti.com

DRV8300

SLVSFG5 – SEPTEMBER 2020

Copyright © 2020 Texas Instruments Incorporated

Submit Document Feedback

21

Product Folder Links: DRV8300