9 Detailed Description

9.1 Overview

The SN74LVC2G08-Q1 device contains two 2-input positive AND gates and performs the Boolean function

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down.

9.2 Functional Block Diagram

1

2

7

1A

1B

1Y

5

6

3

2A

2B

2Y

9.3 Feature Description

9.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

9.3.2 Standard CMOS Inputs

This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically

modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case

resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the

maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).

Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the

input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification

will result in excessive power consumption and could cause oscillations. More details can be found in

Implications of Slow or Floating CMOS Inputs.

Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at

added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,

however a 10-kΩ resistor is recommended and will typically meet all requirements.

9.3.3 Clamp Diode Structure

The inputs and outputs to this device have negative clamping diodes only as depicted in Figure 9-1.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to

the device. The input and output voltage ratings may be exceeded if the input and output clamp-

current ratings are observed.

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SN74LVC2G08-Q1

SCES557E – MARCH 2004 – REVISED OCTOBER 2020

Copyright © 2020 Texas Instruments Incorporated

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