AS5715R datasheet(6/12 Pages) AMSCO

6 / 12 page

Document Feedback

Communication Interface

I²C Communication

Application Note

• PUBLIC

AN000710

• v1-00 • 2020-Jul-21

│ 6

2.2.1

Timing

Figure 4:

Timing

Figure 5 :

I²C Timing

Symbol

Parameter

Min

Max

Unit

fSCLK

SCL clock frequency

1.0

MHz

tBUF

Bus free time (time between the STOP and

START conditions)

0.5

µs

tHD;STA

Hold time; (Repeated) START condition(1)

0.26

µs

tLOW

Low phase of SCL clock

0.5

µs

tHIGH

High phase of SCL clock

0.26

µs

tSU;STA

Setup time for repeated START condition

0.26

µs

tHD;DAT

Data hold time(2)

0.45

µs

tSU;DAT

Data setup time(3)

Rise time of SDA and SCL signals

120

Fall time of SDA and SCL signals

120(4)

tSU;STO

Setup time for STOP condition

0.26

µs

(1)

After this time, the first clock is generated.

(2)

A device must internally provide a minimum hold time of 120 ns (Fast-mode Plus) for the SDA signal (referred to the

VIHmin of SCL).to bridge the undefined region of the falling edge of SCL.

AS5715R Datasheet(PDF) 6 Page - ams AG

AS5715R Datasheet(HTML) 6 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL