STM32WL55JC datasheet(19/145 Pages) STMICROELECTRONICS

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DS13293 Rev 1

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STM32WL55/54xx

Functional overview

3.9

Sub-GHz radio

3.9.1

Introduction

The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM

band. LoRa, (G)FSK/(G)MSK modulation in transmit and receive, and (D)BPSK in transmit

only, allow an optimal trade-off between range, data rate and power consumption. This sub-

GHz radio is compliant with the LoRaWAN® specification v1.0 and radio regulations such as

ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 part 15, 24, 90, 101 and the ARIB

STD-T30, T-67, T-108.

The sub-GHz radio consists of:

•

an analog front-end transceiver, capable of outputting up to + 15 dBm maximum power

on its RFO_LP pin and up to + 22 dBm maximum power on RFO_HP pin

•

a digital modem bank providing the following modulation schemes:

–

LoRa Rx/Tx with bandwidth (BW) from 7.8 - 500 kHz, spreading factor (SF)

5 - 12, bit rate (BR) from 0.013 to 17.4 Kbit/s (real bitrate)

–

FSK and GFSK Rx/Tx with BR from 0.6 to 300 Kbit/s

–

(G)MSK Tx with BR from 0 to 10 Kbit/s

–

BPSK and DBPSK TX only with bitrate for 100 and 600 bit/s

•

a digital control including all data processing and sub-GHz radio configuration control

•

a high-speed clock generation

3.9.2

General description

The sub-GHz radio provides an internal processing unit to handle communication with the

system CPU. Communication is handled by commands sent over the SPI interface, and a

set of interrupts is used to signal events. BUSY information signals operation activity and is

used to indicate when the sub-GHz radio commands cannot be received.

The block diagram of the sub-GHz radio system is shown in the figure below.

Figure 2. sub-GHz radio system block diagram

MSv62614V1

Sub-GHz radio

Sub-GHz

RF frontend

Radio

control

SUBGHZSPI

hse32

Interrups

RFO_LP

RFO_HP

RFI_P

RFI_N

FSK

modem

LoRa

modem

(note)

Data

and

control

HSE32

OSC_IN

OSC_OUT

BUSY

HSERDY

HSEON

HSEBYPPWR

Note: LoRa modem is only available on STM32WL55xx devices.

VR_PA

VDDPA

PB0_VDDTCXO

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