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PLMP7704HBH/EM Datasheet(PDF) 18 Page - Texas Instruments |
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PLMP7704HBH/EM Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 31 page ![]() 7.3.4 Input Capacitance CMOS input stages inherently have low input bias current and higher input-referred voltage noise. The LMP7704-SP enhances this performance by having the low input bias current of only ±200 fA, as well as, a very low input referred voltage noise of 9 nV/√Hz. To achieve these specifications, a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7704-SP. The typical value of this input capacitance, CIN, for the LMP7704-SP is 25 pF. The input capacitance interacts with other impedances, such as gain and feedback resistors, which are seen on the inputs of the amplifier, to form a pole. This pole has little or no effect on the output of the amplifier at low frequencies and dc conditions, but plays a bigger role as the frequency increases. At higher frequencies, the presence of this pole decreases phase margin and also causes gain peaking. To compensate for the input capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The dc gain of the circuit shown in Figure 7-2 is simply –R2/R1. CIN R1 R2 VOUT + - + - VIN + - VOUT VIN R2 R1 AV = - = - CF Figure 7-2. Compensating for Input Capacitance For the time being, ignore CF. The ac gain of the circuit in Figure 7-2 can be calculated as follows: -R2/R1 1 + s ¨ © § + s 2 A0 CIN R2 ¨ © § VOUT VIN (s) = A0 R1 R1 + R2 (1) This equation is rearranged to find the location of the two poles: + ¨ © § -1 2CIN P1,2 = 1 R1 1 R2 r 1 R1 1 R2 + 2 - 4 A0CIN R2 (2) LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LMP7704-SP |
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