ZSSC3224 Datasheet

© 2018 Integrated Device Technology, Inc

13

November 12, 2018

Figure 5.2 ZSSC3224 Functional Block Diagram with Voltage-Source Sensor

AGND / CM

Generator

Bias Current

Generator

Power-On

Reset (POR)

Temperature

Reference

Sensor

DSP Core

(Calculations,

Communication)

MTP

System

Control

Unit

Pre-amplifier

EOC

INP

INN

VDD

VSSB

Oscillator

Clock

Generator

SPI

I2C

SCLK/SCL

MISO

MOSI/SDA

SS

VSS

Voltage Regulator

Power Ctr.

Vreg int

A

D

24-Bit

VDDB

ZSSC3224

RES

The amplifier consists of two stages with programmable gain values.

The ZSSC3224 employs a programmable analog-to-digital converter (ADC) optimized for conversion speed and noise suppression. The

programmable resolution from 12 to 24 bits provides flexibility for adapting the conversion characteristics. To improve power supply noise

is a bridge-type element.

The remaining ZSSC3224-internal offset and the sensor element offset, i.e., the overall system offset for the amplifier and ADC, can be canceled

by means of an offset and auto-zero measurement, respectively.

correction coefficients are stored in the MTP memory.

The ZSSC3224 supports SPI and I2C interface communication for controlling the ZSSC3224, configuration, and measurement result output.

5.3

Analog Front End

5.3.1 Amplifier

The amplifier has a fully differential architecture and consists of two stages. The amplification of each stage and the external sensor gain polarity

section 6.6.2) in the MTP memory (for details, see section 5.4.2).

Note: Only one of these two possible configurations is used for the measurement. The default configuration is SM_config1. Alternately,

SM_config2 can be implemented by sending a command to select this configuration for the measurement (see section 6.5.1). The term

SM_config is used in explanations for general register content and functionality for both SM_config1 and SM_config2, as the registers’ bit

assignments are exactly the same for both registers.

The first 6 bits of SM_config are the programmable gain settings Gain_stage1 and Gain_stage2. The options for the programmable gain settings

are listed in Table 5.1 and Table 5.2.