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ZSSC3224 Datasheet(PDF) 21 Page - Renesas Technology Corp |
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ZSSC3224 Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 48 page ![]() ZSSC3224 Datasheet © 2018 Integrated Device Technology, Inc 21 November 12, 2018 Figure 6.1 Interrupt Functionality 6.4 Operational Modes Figure 6.2 illustrates the ZSSC3224 power-up sequence and subsequent operation depending on the selected interface communication mode (I2C or SPI) as determined by interface-related first activities after power-up or reset. If the first command after power-up is a valid I2C command, the interface will function as an I2C interface until the next power-on reset (POR). If there is no valid I2C command, but an active signal at the SS pin is detected as the first valid activity, then the interface will respond as an SPI slave. With either interface, after the voltage regulators are switched on, the ZSSC3224’s low-voltage section (LV) is active while the related interface configuration information is read from memory. Then the LV section is switched off, the ZSSC3224 goes into Sleep Mode, and the interface is ready to receive commands. The interface is always powered by VDD, so it is referred to as the high voltage section (HV). See Table 6.1 for definitions of the commands. Time Measurement Result 0 max. threshold 1 threshold 2 Time 0 1 EOC / INT Case A: threshold1 > threshold2 Time Measurement Result 0 max. threshold 2 threshold 1 Time 0 1 EOC / INT Case B: threshold1 < threshold2 Time Measurement Result 0 max. threshold 1 Time 0 1 EOC / INT INT_setup=01: Measurement < threshold1 Time Measurement Result 0 max. threshold 1 Time 0 1 EOC / INT INT_setup=10: Measurement > threshold1 INT_setup=11 |
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