Factsheet 05.000

April 2020

These specifications are subject to change without notice.

04/29/2020

© 2020 Greenliant

2

S71461-01

GLS FS0019 Rev. 00

GLS87DPxxxx3 / GLS87BPxxxx3 PX Series

Industrial / Commercial Temp SATA M.2 ArmourDrive™

1.0

GENERAL DESCRIPTION

Each M.2 ArmourDrive module integrates a SATA SSD controller with NAND flash multi-chip packages. Refer to

Figure 2-1 for the M.2 ArmourDrive block diagram.

1.1

Optimized M.2 ArmourDrive

The heart of M.2 ArmourDrive is the SATA SSD

controller, which translates standard SATA signals

into flash media data and control signals. The

following components contribute to M.2 ArmourDrive’s

operation.

1.1.1

Microcontroller Unit (MCU)

The MCU translates SATA commands into data and

control signals required for flash media operation.

1.1.2

Internal Direct Memory Access (DMA)

M.2 ArmourDrive uses internal DMA allowing instant

data transfer from/to buffer to/from flash media. This

implementation eliminates microcontroller overhead

associated

with

the

traditional,

firmware-based

approach, thereby increasing the data transfer rate.

1.1.3

Power Management Unit (PMU)

The PMU controls the power consumption of M.2

ArmourDrive. The PMU dramatically reduces the

power consumption of M.2 ArmourDrive by putting the

part of the circuitry that is not in operation into sleep

mode.

The Flash File System handles inadvertent power

interrupts and has auto-recovery capability to ensure

M.2 ArmourDrive firmware integrity. For regular power

management,

the

host

must

send

an

IDLE_IMMEDIATE command and wait for command

ready before powering down M.2 ArmourDrive.

1.1.4

Embedded Flash File System

The embedded flash file system is an integral part of

M.2 ArmourDrive. It contains MCU firmware that

performs the following tasks:

1.

Translates host side signals into flash media

writes and reads

2.

Provides flash media wear leveling to spread the

flash writes across all memory address space to

increase the longevity of flash media

3.

Keeps track of data file structures

1.1.5

Power Interrupt Data Protection

Power Interrupt Data Protection is a mechanism to

help prevent data corruption during unexpected power

failure events. Enhanced data integrity is supported by

the controller’s advanced firmware during abnormal

power loss. The controller proactively optimizes the

amount and stay time of the “in-flight” data residing in

the cache. To ensure there is no data loss risk caused

by

power

cycling,

the

controller

sends

an

acknowledgement to the host only when the incoming

data is fully committed to the NAND flash.

1.1.6

Error Correction Code (ECC)

The ECC technology uses advanced Low Density

Parity Check (LDPC) algorithms to detect and correct

errors, ensuring data integrity and extending the SSD

lifespan.

1.1.7

Multi-tasking Interface

The multi-tasking interface enables concurrent Read,

Program and Erase operations to multiple NAND flash

media.

1.2

Advanced NAND Management

M.2 ArmourDrive’s controller uses advanced wear-

leveling algorithms to substantially increase the

longevity of NAND flash media. Wear caused by

data writes is evenly distributed in all or select

blocks in the device that prevents “hot spots” in

locations that are programmed and erased

extensively. This effective wear-leveling technique

results in optimized device endurance, enhanced

data retention and higher reliability required by

long-life applications.