F280041PMSR datasheet(64/230 Pages) TI

64 / 230 page

7.9 System

7.9.1 Power Management

TMS320F28004x MCUs can be configured to operate with one of three options to supply the required 1.2 V to

the core (VDD):

• An external supply (not available for 56-pin RSH package configurations)

• Internal 1.2-V LDO Voltage Regulator (VREG)

• Internal 1.2-V Switching Regulator (DC-DC)

The system requirements will dictate which supply option best suits the application.

Note

The same system voltage regulator must be used to drive both VDDIO and VDDIO_SW.

7.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)

The internal VREG is supplied by VDDIO and generates the 1.2 V required to power the VDD pins. Enable this

functionality by pulling the VREGENZ pin low to VSS. The smaller pin-count packages may not include the

VREGENZ pin; therefore, the internal VREG is always enabled and, as such, is the required supply source for

the VDD pins. Review the description of VREGENZ in Table 6-5 to determine package configuration. Although

the internal VREG eliminates the need to use an external power supply for VDD, decoupling capacitors are

required on each VDD pin for VREG stability. There are two recommended capacitor configurations (described in

the list that follows) for the VDD rail when using the internal VREG. The signal description for VDD can be found

in Table 6-4.

• Configuration 1: Place a small decoupling capacitor to VSS on each pin as close to the device as possible. In

addition, a bulk capacitance must be placed on the VDD node to VSS (one 20-µF capacitor or two parallel

10-µF capacitors).

• Configuration 2: Distribute the total capacitance to VSS evenly across all VDD pins (total capacitance divided

by four VDD pins).

7.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)

The internal DC-DC regulator offers increased efficiency over the LDO for converting 3.3 V to 1.2 V. The internal

DC-DC regulator is supplied by the VDDIO_SW pin and generates the 1.2 V required to power the VDD pins. To

use the internal switching regulator, the core domain must power up initially using the internal LDO VREG supply

(tie the VREGENZ pin low to VSS) and then transition to the DC-DC regulator through application software by

setting the DCDCEN bit in the DCDCCTL register. VREGENZ must still be kept low after transition since it

controls both the DC-DC and LDO. Tying VREGENZ high disables both the DC-DC and LDO. The DC-DC

regulator also requires external components (inductor, input capacitance, and output capacitance). The output of

internal DC-DC regulator is not internally fed to the VDD rail and requires an external connection. Figure 7-6

shows the schematic implementation.

CVDDIO_SW

VDDIO_SW

VSS_SW

VSW

VFBSW

VIN

VDD

VSS_SW

CVDD_DECAP

(A)

VSS

VSS_SW

VSS

CVDD

VSS

F28004x

LVSW

VDD

A. One decoupling capacitor per each of the four VDD pins

Figure 7-6. DC-DC Circuit Schematic

TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,

TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C

SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021

www.ti.com

Submit Document Feedback

Product Folder Links: TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C

TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C

F280041PMSR Datasheet(PDF) 64 Page - Texas Instruments

F280041PMSR Datasheet(HTML) 64 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL