F280041PMSR datasheet(90/230 Pages) TI

90 / 230 page

Section 7.9.8.2.4 lists the HALT mode timing requirements, Section 7.9.8.2.5 lists the switching characteristics,

and Figure 7-27 shows the timing diagram for HALT mode.

7.9.8.2.4 HALT Mode Timing Requirements

MIN

MAX

UNIT

tw(WAKE-GPIO)

Pulse duration, GPIO wake-up signal(1)

toscst + 2tc(OSCCLK)

cycles

tw(WAKE-XRS)

Pulse duration, XRSn wake-up signal(1)

toscst + 8tc(OSCCLK)

cycles

(1)

For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/

layout external to the device. See Section 7.9.3.4.2 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,

see Section 7.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is

powered externally to the device.

7.9.8.2.5 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

td(IDLE-XCOS)

Delay time, IDLE instruction executed to XCLKOUT stop

16tc(INTOSC1)

cycles

td(WAKE-HALT)

Delay time, external wake signal end to CPU program

execution resume

cycles

•

Wake up from flash

–

Flash module in active state

75tc(OSCCLK)

•

Wake up from flash

–

Flash module in sleep state

17500tc(OSCCLK) (1)

•

Wake up from RAM

75tc(OSCCLK)

(1)

This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and

FPAC1[PSLEEP]. For more information, see the Flash/OTP and Pump Power Modes and Wakeup section of the TMS320F28004x

Microcontrollers Technical Reference Manual.

7.9.8.2.6 HALT Mode Timing Diagram

OSCCLK

XCLKOUT

HALT

Flushing Pipeline

Device

Status

Normal

Execution

GPIOn

(A)

(C)

(D)(E)

(F)

(B)

(G)

d(IDLE-XCOS)

w(WAKE-GPIO)

d(WAKE-HALT)

Oscillator Start-up Time

A. IDLE instruction is executed to put the device into HALT mode.

B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This

delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,

the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the

zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1 to

TMS320F280049, TMS320F280049C, TMS320F280048, TMS320F280048C, TMS320F280045,

TMS320F280041, TMS320F280041C, TMS320F280040, TMS320F280040C

SPRS945F – JANUARY 2017 – REVISED FEBRUARY 2021

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TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C

F280041PMSR Datasheet(PDF) 90 Page - Texas Instruments

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