UPD78044F datasheet(12/42 Pages) NEC

12 / 42 page

µPD780016Y, 780018Y

3.2 Non-port Pins (2/2)

Low-order address bus at external memory expansion.

High-order address bus at external memory expansion.

External memory read operation strobe signal output.

External memory write operation strobe signal output.

Wait insertion at external memory access.

Strobe output which externally latches the address information output to

ports 4, 5 and 8 to access external memory.

A/D converter analog input.

A/D converter reference voltage input (shared with analog power supply).

A/D converter ground potential. Same potential as VSS0.

System reset input.

Main system clock oscillation crystal connection.

Subsystem clock oscillation crystal connection.

Port block positive power supply.

Port block ground potential.

Positive power supply (except for port and analog blocks)

Ground potential (except for port and analog blocks)

Internal connection. Connect directly to VSS0.

Function

Pin Name

I/O

A0 to A7

A8 to A15

WAIT

ASTB

ANI0 to ANI7

AVREF

AVSS

RESET

XT1

XT2

VDD0

VSS0

VDD1

VSS1

Alternate

Function Pin

Output

P80 to P87

P50 to P57

P64

P65

P66

P67

P10 to P17

—

Output

Input

Output

Input

—

Input

—

Input

—

After

Reset

Input

—

Input

—

UPD78044F Datasheet(PDF) 12 Page - NEC

UPD78044F Datasheet(HTML) 12 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL