ADRF5740

Data Sheet

Rev. 0 | Page 6 of 13

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST

BE CONNECTED TO THE RF AND DC GROUND

OF THE PCB.

VDD

D4

VSS

GND

ATTOUT

1

D5

2

GND

3

ATTIN

4

12

11

10

9

6

5

7

8

16

15

14

13

ADRF5740

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

D4

Parallel Control Input for 8 dB Attenuator Bit. See the Theory of Operation section for more information.

2

D5

Parallel Control Input for 8 dB Attenuator Bit. See the Theory of Operation section for more information.

3, 5 to 8, 10, 14

GND

Ground. The GND pins must be connected to the RF and dc ground of the PCB.

4

ATTIN

Attenuator Input. The ATTIN pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking

capacitor is necessary when the RF line potential is equal to 0 V dc.

9

ATTOUT

Attenuator Output. The ATTOUT pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking

capacitor is necessary when the RF line potential is equal to 0 V dc.

11

VSS

Negative Supply Input.

12

VDD

Positive Supply Input.

13

LE

Latch Enable Input. See the Theory of Operation section for more information.

15

D2

Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information.

16

D3

Parallel Control Input for 4 dB Attenuator Bit. See the Theory of Operation section for more information.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.

INTERFACE SCHEMATICS

ATTIN,

ATTOUT

Figure 5. ATTIN and ATTOUT Interface

VDD

VDD

VDD

330kΩ

LE, D2, D3,

D4, D5

Figure 6. Digital Input Interface (LE, D2, D3, D4, D5)

VDD

GND

GND

CLAMP

Figure 7. VDD Pin Interface Schematic

VSS

GND

GND

CLAMP

Figure 8. VSS Pin Interface Schematic