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ADSP21569WCBCZ10RL Datasheet(PDF) 39 Page - Analog Devices |
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ADSP21569WCBCZ10RL Datasheet(HTML) 39 Page - Analog Devices |
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39 / 104 page  Rev. B | Page 39 of 104 | February 2021 ADSP-21562/21563/21565/21566/21567/21569 DMC0_A11 Output B None None L VDD_DMC Desc: DMC0 Address 11 Notes: No notes DMC0_A12 Output B None None L VDD_DMC Desc: DMC0 Address 12 Notes: No notes DMC0_A13 Output B None None L VDD_DMC Desc: DMC0 Address 13 Notes: No notes DMC0_A14 Output B None None L VDD_DMC Desc: DMC0 Address 14 Notes: No notes DMC0_A15 Output B None None L VDD_DMC Desc: DMC0 Address 15 Notes: No notes DMC0_BA0 Output B None None L VDD_DMC Desc: DMC0 Bank Address Input 0 Notes: No notes DMC0_BA1 Output B None None L VDD_DMC Desc: DMC0 Bank Address Input 1 Notes: No notes DMC0_BA2 Output B None None L VDD_DMC Desc: DMC0 Bank Address Input 2 Notes: No notes DMC0_CAS Output B None None L VDD_DMC Desc: DMC0 column address strobe Notes: No notes DMC0_CK Output C None None L VDD_DMC Desc: DMC0 clock Notes: No notes DMC0_CK Output C None None H VDD_DMC Desc: DMC0 clock (complement) Notes: No notes DMC0_CKE Output B None None L VDD_DMC Desc: DMC0 clock enable Notes: No notes DMC0_CS0 Output B None None L VDD_DMC Desc: DMC0 Chip Select 0 Notes: No notes DMC0_DQ00 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 0 Notes: No notes DMC0_DQ01 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 1 Notes: No notes DMC0_DQ02 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 2 Notes: No notes DMC0_DQ03 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 3 Notes: No notes DMC0_DQ04 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 4 Notes: No notes DMC0_DQ05 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 5 Notes: No notes DMC0_DQ06 InOut B Internal logic ensures that input signal does not float None None VDD_DMC Desc: DMC0 Data 6 Notes: No notes Table 18. ADSP-2156x Designer Quick Reference (Continued) Signal Name Type Driver Type Internal Termination Reset Termination Reset Drive Power Domain Description and Notes |
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