ADSP21569WCBCZ10RL datasheet(6/104 Pages) AD

6 / 104 page

Rev. B

Page 6 of 104

February 2021

ADSP-21562/21563/21565/21566/21567/21569

cache, with the remaining L1 memory configured as SRAM.

Each addressable memory space outside the L1 memory can be

accessed either directly or via cache.

The memory map in Table 2 gives the L1 memory address space

and shows multiple L1 memory blocks offering a configurable

mix of SRAM and cache.

L1 Master and Slave Ports

The SHARC+ core has two master/slave ports to and from the

system fabric. One master port fetches instructions. The second

master port drives data to the system world. Slave Port 1

together with Slave Port 2 memory direct memory access (high

speed MDMA) run conflict free access to the individual mem-

ory blocks. For the slave port addresses, refer to the L1 memory

address map in Table 2.

L1 On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks, assuming no

block conflicts. The total bandwidth is realized using both the

DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit

SYSCLK speed).

Instruction and Data Cache

The ADSP-2156x processors also include a traditional instruc-

tion cache (I-cache) and two data caches (D-caches, one each

for PM/DM) with parity support for all caches. These caches

support one instruction access and two data accesses over the

DM and PM buses per CCLK cycle. The cache controllers auto-

matically manage the configured L1 memory. The system can

configure part of the L1 memory for automatic management by

the cache controllers. The sizes of these caches are inde-

pendently configurable from 0 to 128 kB each. The memory not

managed by the cache controllers is directly addressable by the

processors. The controllers ensure the data coherence between

Figure 3. SHARC+ SIMD Core Block Diagram

SIMD Core

11-STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

PM DATA 64

DM DATA 64

DM ADDRESS 32

DAG1

16 × 32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

PEx

DATA

16 × 40-BIT

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

PEy

DATA

16 × 40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

DAG2

16 × 32

ALU

MULTIPLIER

SHIFTER

DATA

SWAP

SYSTEM

I/F

USTAT

PM ADDRESS 24

PM DATA 48

DEBUG

TRACE

FLAGS

CEC

BTB

CONFLICT

CACHE

IMIF

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