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DSC2021

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MK-Q-B-P-D-12042604-2

DSC2021

Low-Jitter Configurable Dual LVPECL-CMOS Oscillator

Notes:

1.

2.

Output is enabled if Enable pad is floated or not connected.

3.

4.

Output Waveform and Test Circuit figures below define the parameters.

5.

Period Jitter includes crosstalk from adjacent output.

Parameter

Condition

Min.

Typ.

Max.

Unit

2.25

3.6

V

Supply Current

EN pin low – outputs are disabled

21

23

mA

EN pin high – outputs are enabled

62

mA

Frequency Stability

Δf

Includes frequency variations due

to initial tolerance, temp. and

power supply voltage

±10

±25

±50

ppm

Aging

Δf

1 year @25°C

±5

ppm

T=25°C

5

ms

Input Logic Levels

Input logic high

Input logic low

-

-

V

5

ns

Output Enable Time

20

ns

Pull-up exists on all digital IO

40

kΩ

LVPECL Output

Output Logic Levels

Output logic high

Output logic low

-

-

V

Pk to Pk Output Swing

Single-Ended

800

mV

Rise Time

Fall Time

20% to 80%

250

ps

Frequency

Single Frequency

2.3

460

MHz

Output Duty Cycle

SYM

Differential

48

52

%

2.5

Integrated Phase Noise

200kHz to 20MHz @156.25MHz

100kHz to 20MHz @156.25MHz

12kHz to 20MHz @156.25MHz

0.25

0.38

1.7

2

CMOS Output

Output Logic Levels

Output logic high

Output logic low

I=±6mA

-

-

V

Rise Time

Fall Time

20% to 80%

1.1

1.3

2

2

ns

Frequency

Commercial/Industrial temp range

2.3

170

MHz

Output Duty Cycle

SYM

45

55

%

3

Integrated Phase Noise

200kHz to 20MHz @ 125MHz

100kHz to 20MHz @ 125MHz

12kHz to 20MHz @ 125MHz

0.3

0.38

1.7

2