THS4281DBVT datasheet(22/31 Pages) TI

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Power Supply Decoupling Techniques and

BOARD LAYOUT

THS4281

SLOS432 – APRIL 2004

Metal-film, axial-lead resistors can also provide

Recommendations

good high frequency performance. Again, keep

their leads and PC board trace length as short as

Power supply decoupling is a critical aspect of any

possible. Never use wire wound type resistors in

high-performance amplifier design. Careful decoup-

a high frequency application. Because the output

ling provides higher quality ac performance. The

pin and inverting input pin are the most sensitive

following guidelines ensure the highest level of per-

to parasitic capacitance, always position the

formance.

feedback and series output resistor, if any, as

1. Place decoupling capacitors as close to the

close as possible to the output pin. Other network

power supply inputs as possible, with the goal of

components, such as noninverting input termin-

minimizing the inductance.

ation resistors, should also be placed close to the

package. Excessively high resistor values can

2. Placement priority should put the smallest valued

create significant phase lag that can degrade

capacitors closest to the device.

performance. Keep resistor values as low as

3. Use of solid power and ground planes is rec-

possible, consistent with load-driving consider-

ommended to reduce the inductance along power

ations. It is suggested that a good starting point

supply return current paths (with the exception of

for design is to set the Rf to 2 kΩ for low-gain,

the areas underneath the input and output pins

noninverting applications. Doing this automati-

as noted below).

cally keeps the resistor noise terms reasonable

4. A bulk decoupling capacitor is recommended (6.8

and minimizes the effect of parasitic capacitance.

to 22 µF) within 1 inch, and a ceramic (0.1 µF)

4. Connections to other wideband devices on

within 0.1 inch of the power input pins.

the board should be made with short direct

traces or through onboard transmission lines.

NOTE:

For short connections, consider the trace and the

input to the next device as a lumped capacitive

The bulk capacitor may be

load. Relatively wide traces (50 mils to 100 mils)

shared by other op amps.

should be used, preferably with ground and

power planes opened up around them. Estimate

the total capacitive load and set RISO from the

plot of recommended RISO vs capacitive load.

Achieving optimum performance with a high fre-

Low parasitic capacitive loads (<4 pF) may not

quency amplifier like the THS4281 requires careful

need an R(ISO), because the THS4281 is nom-

attention to board layout parasitics and external

inally compensated to operate at unity gain (+1

component types. See the EVM layout figures in the

V/V) with a 2-pF capacitive load. Higher capaci-

Design Tools Section.

tive loads without an R(ISO) are allowed as the

Recommendations that optimize performance include:

signal gain increases. If a long trace is required,

1. Minimize parasitic capacitance to any ac

and the 6-dB signal loss intrinsic to a doubly

ground for all of the signal I/O pins. Parasitic

terminated transmission line is acceptable, im-

capacitance on the output and inverting input pins

plement a matched impedance transmission line

can cause instability and on the noninverting

using microstrip or stripline techniques (consult

input, it can react with the source impedance to

an ECL design handbook for microstrip and

cause unintentional band limiting. To reduce un-

stripline layout techniques). A matching series

wanted capacitance, a window around the signal

resistor into the trace from the output of the

I/O pins should be opened in all of the ground

THS4281 is used as well as a terminating shunt

and power planes around those pins. Otherwise,

resistor at the input of the destination device.

ground and power planes should be unbroken

Remember also that the terminating impedance is

elsewhere on the board.

the parallel combination of the shunt resistor and

the input impedance of the destination device:

2. Minimize the distance (< 0.1 inch) from the

this total effective impedance should be set to

power supply pins to high frequency 0.1-µF

match the trace impedance. If the 6-dB attenu-

decoupling capacitors. Avoid narrow power and

ation of a doubly terminated transmission line is

ground traces to minimize inductance. The power

unacceptable,

long

trace

can

supply connections should always be decoupled

series-terminated at the source end only. Treat

as described above.

the trace as a capacitive load in this case, and

3. Careful selection and placement of external

set the series resistor value as shown in the plot

components preserves the high frequency

of R(ISO) vs capacitive load. If the input im-

performance of the THS4281. Resistors should

pedance of the destination device is low, there is

be a low reactance type. Surface-mount resistors

signal attenuation due to the voltage divider

work best and allow a tighter overall layout.

formed by R(ISO) into the terminating impedance.

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