MSP430F2012IPW datasheet(24/80 Pages) TI

24 / 80 page

MSP430x20x1, MSP430x20x2, MSP430x20x3

MIXED SIGNAL MICROCONTROLLER

SLAS491A − AUGUST 2005 − REVISED OCTOBER 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

outputs − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

I(OHmax) = −1.5 mA (see Notes 1)

2.2 V

VCC−0.25

VCC

VOH

High-level output

I(OHmax) = −6 mA (see Notes 2)

2.2 V

VCC−0.6

VCC

VOH

High-level output

voltage

I(OHmax) = −1.5 mA (see Notes 1)

3 V

VCC−0.25

VCC

voltage

I(OHmax) = −6 mA (see Notes 2)

3 V

VCC−0.6

VCC

I(OLmax) = 1.5 mA (see Notes 1)

2.2 V

VSS

VSS+0.25

VOL

Low-level output

I(OLmax) = 6 mA (see Notes 2)

2.2 V

VSS

VSS+0.6

VOL

Low-level output

voltage

I(OLmax) = 1.5 mA (see Notes 1)

3 V

VSS

VSS+0.25

I(OLmax) = 6 mA (see Notes 2)

3 V

VSS

VSS+0.6

NOTES:

1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum

voltage drop specified.

2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum

voltage drop specified.

output frequency − Ports P1 and P2

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

fPx.y

Port output frequency

P1.4/SMCLK, CL = 20 pF, RL = 1 kOhm

2.2 V

MHz

fPx.y

Port output frequency

(with load)

P1.4/SMCLK, CL = 20 pF, RL = 1 kOhm

(see Note 1 and 2)

3 V

MHz

fPort_CLK

Clock output frequency

P2.0/ACLK, P1.4/SMCLK, CL = 20 pF

2.2 V

MHz

fPort_CLK

Clock output frequency

P2.0/ACLK, P1.4/SMCLK, CL = 20 pF

(see Note 2)

3 V

MHz

NOTES:

1. A resistive divider with 2 times 0.5 k

W between VCC and VSS is used as load. The output is connected to the center tap of the divider.

2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

MSP430F2012IPW Datasheet(PDF) 24 Page - Texas Instruments

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