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PSD813F1V-90UT Datasheet(PDF) 87 Page - STMicroelectronics |
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PSD813F1V-90UT Datasheet(HTML) 87 Page - STMicroelectronics |
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87 / 110 page ![]() 87/110 PSD813F1V Figure 46. Input Macrocell Timing (product term clock) Table 53. Input Macrocell Timing (5V devices) Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. 2. ZPSD versions only. Table 54. Input Macrocell Timing (3V Devices) Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. 2. ZPSD Versions only. Symbol Parameter Conditions -90 -12 -15 PT Aloc Turbo Off2 Unit Min Max Min Max Min Max tIS Input Setup Time (Note 1) 00 0 ns tIH Input Hold Time (Note 1) 20 22 26 + 10 ns tINH NIB Input High Time (Note 1) 12 15 18 ns tINL NIB Input Low Time (Note 1) 12 15 18 ns tINO NIB Input to Combinatorial Delay (Note 1) 46 50 59 + 2 + 10 ns Symbol Parameter Conditions -15 -20 PT Aloc Turbo Off2 Unit Min Max Min Max tIS Input Setup Time (Note 1) 00 ns tIH Input Hold Time (Note 1) 25 30 + 20 ns tINH NIB Input High Time (Note 1) 13 15 ns tINL NIB Input Low Time (Note 1) 13 15 ns tINO NIB Input to Combinatorial Delay (Note 1) 62 70 + 4 + 20 ns tINH tINL tINO tIH tIS PT CLOCK INPUT OUTPUT AI03101 |
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