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ADGS1209 Datasheet(PDF) 12 Page - Analog Devices

Part # ADGS1209
Description  SPI Interface, Low CON and QINJ, 짹15 V/12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches
PDF  33 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADGS1209 Datasheet(HTML) 12 Page - Analog Devices

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ADGS1208/ADGS1209
Data Sheet
Rev. 0 | Page 12 of 33
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
S3
S2
S1
VSS
GPO2
GPO1
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS.
2. NIC = NOT INTERNALLY CONNECTED.
S6
S5
VDD
GND
CNV
GPO3
ADGS1208
TOP VIEW
(Not to Scale)
Figure 7. ADGS1208 Pin Configuration
Table 8. ADGS1208 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
GPO1
General-Purpose Output 1. This pin is a digital output.
2
GPO2
General-Purpose Output 2. This pin is a digital output.
3
VSS
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
4
S1
Source Terminal 1. This pin can be an input or output.
5
S2
Source Terminal 2. This pin can be an input or output.
6
S3
Source Terminal 3. This pin can be an input or output.
7
S4
Source Terminal 4. This pin can be an input or output.
8, 10
NIC
Not Internally Connected. These pins are not connected internally.
9
D
Drain Terminal. This pin can be an input or output.
11
S8
Source Terminal 8. This pin can be an input or output.
12
S7
Source Terminal 7. This pin can be an input or output.
13
S6
Source Terminal 6. This pin can be an input or output.
14
S5
Source Terminal 5. This pin can be an input or output.
15
VDD
Most Positive Power Supply Potential.
16
GND
Ground (0 V) Reference.
17
CNV
Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels.
18
GPO3
General-Purpose Output 3. This pin is a digital output.
19
SDO
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
20
RESET/VL
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate
registers are set to their default values.
21
CS
Active Low Control Input. CS is the frame synchronization signal for the input data.
22
SCLK
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
23
SDI
Serial Data Input. Data is captured on the positive edge of the serial clock input.
24
GPO4
General-Purpose Output 4. This pin is a digital output.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.



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