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MUX

9−Bit Divider M

1 .. 511

PLLx

12−Bit Divider N

1 .. 4095

PFD

Filter

VCO

SSC

(PLL2 only)

Input Clock

Programming

PLL output

SSC output

(PLL2 Only)

VCO Bypass

Spread Spectrum Clocking and EMI Reduction

CDCE706

SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005

Figure 13. PLL Architecture

All three PLLs are designed for easiest configuration. The user just has to define the input and output

frequencies or the divider (M, N, P) setting respectively. All other parameters, such as charge-pump current, filter

components, phase margin, or loop bandwidth are controlled and set by the device itself. This assures optimized

jitter attenuation and loop stability.

The PLL support normal-speed mode (80 MHz

≤ f

VCO≤ 167 MHz) and high-speed mode (150 MHz ≤ fVCO≤ 300

MHz) which can be selected by PLLxFVCO (Bit [7:5] of Byte 6). The respective speed option assures stable

operation and lowest jitter.

The divider M and divider N operates internally as fractional divider for fVCO up to 250 MHz. This allows fractional

divider ratio for zero ppm output clock error.

In case of fVCO > 250 MHz, it is recommended that integer factors of N/M are used only.

For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept

requires a PPL divider configuration, M

≤ N (or N/M ≥ 1).

Additionally, each PLL supports two bypass options:

•

PLL Bypass and

•

VCO Bypass

In PLL bypass mode, the PLL completely is bypassed, so that the input clock is switched directly to the

Output-Switch-A (SWAPxx of Byte 9 to12). In the VCO bypass mode, only the VCO of the respective PLL is

bypassed by setting PLLxMUX to 1 (Bit [7:5] of Byte 3). But the divider M still is useable and expands the output

divider by additional 9-bits. This gives a total divider range of M x P = 511

× 127 = 64897. In VCO bypass mode

the respective PLL block is powered down and minimizes current consumption.

Table 3. Example for Divide, Multiplication, and Bypass Operation

Function

Equation(1)

fIN

fOUT-desired

fOUT-actual

Divider

fVCO [MHz]

[MHz]

N/M

Fractional(2)

fOUT = fIN x (N/M)/P

30.72

155.52

5.0625

155.52

Integer Factor(3)

fOUT = fIN x (N/M)/P

270

VCO bypass

fOUT = fIN/(M x P)

30.72

0.06

—

(1)

P-divider of Output-Switch-Matrix is included in the calculation.

(2)

Fractional operation for fVCO≤ 250 MHz.

(3)

Integer operation for fVCO > 250 MHz.

In addition to the basic PLL function, PLL2 supports spread spectrum clocking (SSC) as well. Thus, PLL 2

features two outputs, a SSC output and a non-SSC output. Both outputs can be used in parallel. The mean

phase of the Center Spread SSC modulated signal is equal to the phase of the non-modulated input frequency.

SSC is selected by Output-Switch-A (SWAPxx of Byte 9 to 12).

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