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DSPIC30F2012 Datasheet(PDF) 200 Page - Microchip Technology |
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DSPIC30F2012 Datasheet(HTML) 200 Page - Microchip Technology |
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200 / 207 page  dsPIC30F2011/2012/3012/3013 DS70139C-page 198 Preliminary © 2005 Microchip Technology Inc. Programmer’s Model........................................................... 18 Diagram ...................................................................... 19 Programming Operations .................................................... 49 Algorithm for Program Flash ....................................... 49 Erasing a Row of Program Memory ............................ 49 Initiating the Programming Sequence ......................... 50 Loading Write Latches ................................................ 50 Protection Against Accidental Writes to OSCCON ........... 122 R Reset......................................................................... 117, 123 BOR, Programmable................................................. 125 Brown-out Reset (BOR) ............................................ 117 Oscillator Start-up Timer (OST) ................................ 117 POR Operating without FSCM and PWRT ................ 125 With Long Crystal Start-up Time....................... 125 POR (Power-on Reset) ............................................. 123 Power-on Reset (POR) ............................................. 117 Power-up Timer (PWRT) .......................................... 117 Reset Sequence.................................................................. 65 Reset Sources ............................................................ 65 Reset Sources Brown-out Reset (BOR) .............................................. 65 Illegal Instruction Trap................................................. 65 Trap Lockout ............................................................... 65 Uninitialized W Register Trap ..................................... 65 Watchdog Time-out..................................................... 65 Reset Timing Characteristics ............................................ 163 Reset Timing Requirements.............................................. 164 Run-Time Self-Programming (RTSP) ................................. 47 S Simple Capture Event Mode ............................................... 81 Buffer Operation.......................................................... 82 Hall Sensor Mode ....................................................... 82 Prescaler ..................................................................... 81 Timer2 and Timer3 Selection Mode ............................ 82 Simple OC/PWM Mode Timing Requirements.................. 169 Simple Output Compare Match Mode................................. 86 Simple PWM Mode ............................................................. 86 Input Pin Fault Protection............................................ 86 Period.......................................................................... 87 Software Simulator (MPLAB SIM)..................................... 140 Software Simulator (MPLAB SIM30)................................. 140 Software Stack Pointer, Frame Pointer............................... 18 CALL Stack Frame...................................................... 37 SPI Module.......................................................................... 89 Framed SPI Support ................................................... 90 Operating Function Description .................................. 89 Operation During CPU Idle Mode ............................... 91 Operation During CPU Sleep Mode ............................ 91 SDOx Disable ............................................................. 90 Slave Select Synchronization ..................................... 91 SPI1 Register Map ...................................................... 92 Timing Characteristics Master Mode (CKE = 0) .................................... 173 Master Mode (CKE = 1) .................................... 174 Slave Mode (CKE = 1) .............................. 175, 176 Timing Requirements Master Mode (CKE = 0) .................................... 173 Master Mode (CKE = 1) .................................... 174 Slave Mode (CKE = 0) ...................................... 175 Slave Mode (CKE = 1) ...................................... 177 Word and Byte Communication .................................. 90 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 1 ...................... 126 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 2 ...................... 126 Status Register ................................................................... 18 Symbols Used in Opcode Descriptions ............................ 132 System Integration Register Map ............................................................ 130 T Table Instruction Operation Summary ................................ 47 Temperature and Voltage Specifications AC............................................................................. 157 DC ............................................................................ 145 Timer 2/3 Module ................................................................ 75 Timer1 Module .................................................................... 71 16-bit Asynchronous Counter Mode ........................... 71 16-bit Synchronous Counter Mode ............................. 71 16-bit Timer Mode....................................................... 71 Gate Operation ........................................................... 72 Interrupt ...................................................................... 72 Operation During Sleep Mode .................................... 72 Prescaler .................................................................... 72 Real-Time Clock ......................................................... 72 Interrupts ............................................................ 73 Oscillator Operation............................................ 73 Register Map .............................................................. 74 Timer2 and Timer3 Selection Mode.................................... 86 Timer2/3 Module 16-bit Timer Mode....................................................... 75 32-bit Synchronous Counter Mode ............................. 75 32-bit Timer Mode....................................................... 75 ADC Event Trigger...................................................... 78 Gate Operation ........................................................... 78 Interrupt ...................................................................... 78 Operation During Sleep Mode .................................... 78 Register Map .............................................................. 79 Timer Prescaler .......................................................... 78 Timing Characteristics A/D Conversion Low-speed (ASAM = 0, SSRC = 000) .............. 185 Bandgap Start-up Time............................................. 164 CAN Module I/O........................................................ 182 CLKOUT and I/O ...................................................... 162 DCI Module AC-Link Mode ................................................... 172 Multichannel, I2S Modes................................... 170 External Clock........................................................... 157 I2C Bus Data Master Mode..................................................... 178 Slave Mode....................................................... 180 I2C Bus Start/Stop Bits Master Mode..................................................... 178 Slave Mode....................................................... 180 Input Capture (CAPX)............................................... 168 OC/PWM Module...................................................... 169 Oscillator Start-up Timer........................................... 163 Output Compare Module .......................................... 168 Power-up Timer ........................................................ 163 Reset ........................................................................ 163 SPI Module Master Mode (CKE = 0).................................... 173 Master Mode (CKE = 1).................................... 174 Slave Mode (CKE = 0)...................................... 175 Slave Mode (CKE = 1)...................................... 176 |
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