DSPIC30F2012 datasheet(201/207 Pages) MICROCHIP

201 / 207 page

Preliminary

DS70139C-page 199

dsPIC30F2011/2012/3012/3013

Type A, B and C Timer External Clock ..................... 165

Watchdog Timer........................................................ 163

Timing Diagrams

PWM Output ............................................................... 87

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 1...................... 124

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 2...................... 124

Time-out Sequence on Power-up

(MCLR Tied to VDD).......................................... 124

Timing Diagrams and Specifications

DC Characteristics - Internal RC Accuracy............... 159

Timing Diagrams.See Timing Characteristics

Timing Requirements

A/D Conversion

Low-speed ........................................................ 186

Bandgap Start-up Time............................................. 165

Brown-out Reset ....................................................... 164

CAN Module I/O........................................................ 182

CLKOUT and I/O....................................................... 162

DCI Module

AC-Link Mode ................................................... 172

Multichannel, I2S Modes ................................... 171

External Clock........................................................... 158

I2C Bus Data (Master Mode)..................................... 179

I2C Bus Data (Slave Mode)....................................... 181

Input Capture ............................................................ 168

Oscillator Start-up Timer ........................................... 164

Output Compare Module........................................... 168

Power-up Timer ........................................................ 164

Reset......................................................................... 164

Simple OC/PWM Mode ............................................. 169

SPI Module

Master Mode (CKE = 0) .................................... 173

Master Mode (CKE = 1) .................................... 174

Slave Mode (CKE = 0) ...................................... 175

Slave Mode (CKE = 1) ...................................... 177

Type A Timer External Clock .................................... 166

Type B Timer External Clock .................................... 167

Type C Timer External Clock .................................... 167

Watchdog Timer........................................................ 164

Timing Specifications

PLL Clock.................................................................. 159

Trap Vectors ....................................................................... 67

UART Module

Address Detect Mode ............................................... 105

Auto Baud Support ................................................... 106

Baud Rate Generator ............................................... 105

Enabling and Setting Up ........................................... 103

Framing Error (FERR) .............................................. 105

Idle Status................................................................. 105

Loopback Mode ........................................................ 105

Operation During CPU Sleep and Idle Modes.......... 106

Overview................................................................... 101

Parity Error (PERR) .................................................. 105

Receive Break .......................................................... 105

Receive Buffer (UxRXB)........................................... 104

Receive Buffer Overrun Error (OERR Bit) ................ 104

Receive Interrupt ...................................................... 104

Receiving Data ......................................................... 104

Receiving in 8-bit or 9-bit Data Mode ....................... 104

Reception Error Handling ......................................... 104

Transmit Break ......................................................... 104

Transmit Buffer (UxTXB) .......................................... 103

Transmit Interrupt ..................................................... 104

Transmitting Data ..................................................... 103

Transmitting in 8-bit Data Mode ............................... 103

Transmitting in 9-bit Data Mode ............................... 103

UART1 Register Map ............................................... 107

UART2 Register Map ............................................... 107

UART Operation

Idle Mode .................................................................. 106

Sleep Mode .............................................................. 106

Unit ID Locations .............................................................. 117

Universal Asynchronous Receiver Transmitter

(UART) Module......................................................... 101

Wake-up from Sleep ......................................................... 117

Wake-up from Sleep and Idle ............................................. 68

Watchdog Timer

Timing Characteristics .............................................. 163

Timing Requirements ............................................... 164

Watchdog Timer (WDT)............................................ 117, 127

Enabling and Disabling ............................................. 127

Operation .................................................................. 127

WWW Address ................................................................. 201

WWW, On-Line Support ....................................................... 7

DSPIC30F2012 Datasheet(PDF) 201 Page - Microchip Technology

DSPIC30F2012 Datasheet(HTML) 201 Page - Microchip Technology

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