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DSPIC30F2012 Datasheet(PDF) 197 Page - Microchip Technology |
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DSPIC30F2012 Datasheet(HTML) 197 Page - Microchip Technology |
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197 / 207 page ![]() © 2005 Microchip Technology Inc. Preliminary DS70139C-page 195 dsPIC30F2011/2012/3012/3013 INDEX Numerics 12-bit Analog-to-Digital Converter (A/D) Module .............. 109 A A/D .................................................................................... 109 Aborting a Conversion .............................................. 111 ADCHS Register ....................................................... 109 ADCON1 Register..................................................... 109 ADCON2 Register..................................................... 109 ADCON3 Register..................................................... 109 ADCSSL Register ..................................................... 109 ADPCFG Register..................................................... 109 Configuring Analog Port Pins.............................. 58, 113 Connection Considerations....................................... 113 Conversion Operation ............................................... 110 Effects of a Reset...................................................... 112 Operation During CPU Idle Mode ............................. 112 Operation During CPU Sleep Mode .......................... 112 Output Formats ......................................................... 112 Power-down Modes .................................................. 112 Programming the Sample Trigger............................. 111 Register Map............................................................. 115 Result Buffer ............................................................. 110 Sampling Requirements............................................ 111 Selecting the Conversion Clock ................................ 111 Selecting the Conversion Sequence......................... 110 AC Characteristics ............................................................ 157 Load Conditions ........................................................ 157 AC Temperature and Voltage Specifications .................... 157 Address Generator Units .................................................... 41 Alternate Vector Table ........................................................ 67 Analog-to-Digital Converter. See A/D. Assembler MPASM Assembler................................................... 139 Automatic Clock Stretch...................................................... 96 During 10-bit Addressing (STREN = 1)....................... 96 During 7-bit Addressing (STREN = 1)......................... 96 Receive Mode ............................................................. 96 Transmit Mode ............................................................ 96 B Bandgap Start-up Time Requirements............................................................ 165 Timing Characteristics .............................................. 164 Barrel Shifter ....................................................................... 25 Bit-Reversed Addressing .................................................... 44 Example ...................................................................... 45 Implementation ........................................................... 44 Modifier Values Table ................................................. 45 Sequence Table (16-Entry)......................................... 45 Block Diagrams 12-bit A/D Functional ................................................ 109 16-bit Timer1 Module .................................................. 71 16-bit Timer2............................................................... 77 16-bit Timer3............................................................... 77 32-bit Timer2/3............................................................ 76 DSP Engine ................................................................ 22 dsPIC30F2011 ............................................................ 10 dsPIC30F2012 ............................................................ 11 dsPIC30F3013 ............................................................ 13 External Power-on Reset Circuit............................... 125 I2C............................................................................... 94 Input Capture Mode .................................................... 81 Oscillator System...................................................... 119 Output Compare Mode ............................................... 85 Reset System ........................................................... 123 Shared Port Structure ................................................. 57 SPI.............................................................................. 89 SPI Master/Slave Connection..................................... 90 UART Receiver......................................................... 102 UART Transmitter..................................................... 101 BOR Characteristics ......................................................... 156 BOR. See Brown-out Reset. Brown-out Reset Characteristics.......................................................... 155 Timing Requirements ............................................... 164 C C Compilers MPLAB C17 .............................................................. 140 MPLAB C18 .............................................................. 140 MPLAB C30 .............................................................. 140 CAN Module I/O Timing Characteristics ........................................ 182 I/O Timing Requirements.......................................... 182 CLKOUT and I/O Timing Characteristics.......................................................... 162 Requirements ........................................................... 162 Code Examples Data EEPROM Block Erase ....................................... 54 Data EEPROM Block Write ........................................ 56 Data EEPROM Read.................................................. 53 Data EEPROM Word Erase ....................................... 54 Data EEPROM Word Write ........................................ 55 Erasing a Row of Program Memory ........................... 49 Initiating a Programming Sequence ........................... 50 Loading Write Latches ................................................ 50 Code Protection ................................................................ 117 Control Registers ................................................................ 48 NVMADR .................................................................... 48 NVMADRU ................................................................. 48 NVMCON.................................................................... 48 NVMKEY .................................................................... 48 Core Architecture Overview..................................................................... 17 CPU Architecture Overview ................................................ 17 Customer Change Notification Service............................. 201 Customer Notification Service .......................................... 201 Customer Support..................................................... 201, 202 D Data Accumulators and Adder/Subtractor .......................... 23 Data Space Write Saturation ...................................... 25 Overflow and Saturation ............................................. 23 Round Logic ............................................................... 24 Write Back .................................................................. 24 Data Address Space........................................................... 33 Alignment.................................................................... 36 Alignment (Figure) ...................................................... 36 Effect of Invalid Memory Accesses (Table) ................ 36 MCU and DSP (MAC Class) Instructions Example .... 35 Memory Map......................................................... 33, 34 Near Data Space ........................................................ 37 Software Stack ........................................................... 37 Spaces........................................................................ 36 Width .......................................................................... 36 Data EEPROM Memory...................................................... 53 Erasing ....................................................................... 54 Erasing, Block............................................................. 54 |
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