LSM6DSO32X datasheet(27/162 Pages) STMICROELECTRONICS

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5.3

I²C/I3C coexistence in LSM6DSO32X

In the LSM6DSO32X, the SDA and SCL lines are common to both I²C and MIPI I3CSM. The I²C bus requires

anti-spike filters on the SDA and SCL pins that are not compatible with MIPI I3CSM timing.

The device can be connected to both I²C and MIPI I3CSM or only to the MIPI I3CSM bus depending on the

connection of the INT1 pin when the device is powered up:

•

INT1 pin floating (internal pull-down): I²C / MIPI I3CSM both active, see Figure 14;

•

INT1 pin connected to Vdd_IO: only MIPI I3CSM active, see Figure 15.

Figure 14. I²C and MIPI I3CSM both active (INT1 pin not connected)

Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave

is addressed, the I²C slave is disabled and the timing is compatible with MIPI I3CSM specifications.

Figure 15. Only MIPI I3CSM active (INT1 pin connected to Vdd_IO)

I²C/I3C

I3C bus case

Dynamic

Address

Assignment

Master resets

I3C private R/W with and without 7Eh

CCC commands

Slave event management

Error detection and recovery

(1)

INT1 pin connected to Vdd_IO

Only I3C active

When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using MIPI I3CSM

SDR timing.

LSM6DSO32X

I²C/I3C coexistence in LSM6DSO32X

DS13607 - Rev 1

page 27/162

LSM6DSO32X Datasheet(PDF) 27 Page - STMicroelectronics