M28F420 datasheet(26/38 Pages) STMICROELECTRONICS

26 / 38 page

Memory Blocks

The memory blocks of the M28F410 and M28F420

are shown in Figure 10. The differencebetween the

two productsis simply an inversion of the block map

to position the Boot Block at the top or bottom of

the memory. The selection of the Boot Block at the

top or bottom of the memory depends on the

microprocessor needs.

Each block of the memory can be erased sepa-

rately, but only by one block at a time. The erase

operation is managed by the P/E.C. but can be

suspended in order to read from another block and

then resumed.

Programming and erasure of the memory is dis-

abled when the program supply is at VPPL. For

successful programming and erasure the program

supply must be at VPPH.

The Boot Block provides additional hardware secu-

rity by use of the RP signal which must be at VHH

before any program or erase operation will be

executed by the P/E.C. on the Boot Block.

Operations

Operations are defined as specific bus cycles and

signals which allow memory Read, Command

Write, Output Disable, Standby, Power Down, and

Electronic Signature Read. They are shown in Ta-

ble 3.

Read. Read operations are used to output the

contents of the Memory Array, the Status Register

or the Electronic Signature. Both Chip Enable E

and Output Enable G must be low in order to read

the output of the memory. The Chip Enable input

also provides power control and should be used for

device selection. Output Enable should be used to

gate data onto the output independentof the device

selection. A read operation will output either a byte

or a word depending on the BYTE signal level.

When BYTE is Low the output byte is on DQ0-DQ7,

DQ8-DQ14 are Hi-Z and A-1 is an additional ad-

dress input. When BYTE is High the output word is

on DQ0-DQ15.

The data read depends on the previous command

written to the memory (see instructions RD, RSR

and RSIG).

8K BOOT BLOCK

AI01277

3FFFFh

3E000h

3DFFFh

3D000h

3CFFFh

3C000h

3BFFFh

00000h

4K PARAMETER BLOCK

48K MAIN BLOCK

64K MAIN BLOCK

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

A0-A17

Word Wide

M28F410 TOP BOOT BLOCK

8K BOOT BLOCK

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

00000h

4K PARAMETER BLOCK

48K MAIN BLOCK

64K MAIN BLOCK

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

A0-A17

Word Wide

M28F420 BOTTOM BOOT BLOCK

Figure 10. Memory Map, Word-wide Addresses

26/38

M28F410, M28F420

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