M50FLW040A datasheet(10/52 Pages) STMICROELECTRONICS

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M50FLW040A, M50FLW040B

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SIGNAL DESCRIPTIONS

There are two distinct bus interfaces available on

this device. The active interface is selected before

power-up, or during Reset, using the Interface

Configuration Pin, IC.

The signals for each interface are discussed in the

Firmware Hub/Low Pin Count (FWH/LPC) Signal

Descriptions section and the Address/Address

Multiplexed (A/A Mux) Signal Descriptions sec-

tion, respectively, while the supply signals are dis-

cussed in the Supply Signal Descriptions section.

Firmware Hub/Low Pin Count (FWH/LPC)

Signal Descriptions

Please see Figure 2. and Table 1..

Input/Output Communications (FWH0/LAD0-

FWH3/LAD3). All Input and Output Communica-

tions with the memory take place on these pins.

Addresses and Data for Bus Read and Bus Write

operations are encoded on these pins.

Input

Communication

Frame

(FWH4/

LFRAME). The

Input

Communication

Frame

(FWH4/LFRAME) signal indicates the start of a

bus operation. When Input Communication Frame

is Low, VIL, on the rising edge of the Clock, a new

bus operation is initiated. If Input Communication

Frame is Low, VIL, during a bus operation then the

operation is aborted. When Input Communication

Frame is High, VIH, the current bus operation is ei-

ther proceeding or the bus is idle.

Identification Inputs (ID0-ID3). Up to 16 memo-

ries can be addressed on a bus, in the Firmware

Hub (FWH) mode. The Identification Inputs allow

each device to be given a unique 4-bit address. A

‘0’ is signified on a pin by driving it Low, VIL, or

leaving it floating (since there is an internal pull-

down resistor, with a value of RIL). A ‘1’ is signified

on a pin by driving it High, VIH (and there will be a

leakage current of ILI2 through the pin).

By convention, the boot memory must have ad-

dress ‘0000’, and all additional memories are giv-

en addresses, allocated sequentially, from ‘0001’.

In the Low Pin Count (LPC) mode, the identifica-

tion Inputs (ID0-ID2) can address up to 8 memo-

ries on a bus. In the LPC mode, the ID3 pin is

Reserved for Future Use (RFU). The value on ad-

dress A19-A21 is compared to the hardware strap-

ping on the ID0-ID2 pins to select the memory that

is being addressed. For an address bit to be ‘1’,

the corresponding ID pin can be left floating or

driven Low, VIL (again, with the internal pull-down

resistor, with a value of RIL). For an address bit to

be ‘0’, the corresponding ID pin must be driven

High, VIH (and there will be a leakage current of

ILI2 through the pin, as specified in Table 24.). For

details, see Table 5..

General Purpose Inputs (GPI0-GPI4). The

General Purpose Inputs can be used as digital in-

puts for the CPU to read, with their contents being

available in the General Purpose Inputs Register.

The pins must have stable data throughout the en-

tire cycle that reads the General Purpose Input

High, VIH, and must not be left floating.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the FWH/LPC in-

terface or the Address/Address Multiplexed (A/A

Mux) Interface is used. The state of the Interface

Configuration, IC, should not be changed during

operation of the memory device, except for select-

ing the desired interface in the period before pow-

er-up or during a Reset.

To select the FWH/LPC Interface, the Interface

Configuration pin should be left to float or driven

Low, VIL. To select the Address/Address Multi-

plexed (A/A Mux) Interface, the pin should be driv-

en High, VIH. An internal pull-down resistor is

included with a value of RIL; there will be a leakage

current of ILI2 through each pin when pulled to VIH.

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the device. When Interface

Reset (RP) is driven Low, VIL, the memory is in

Reset mode (the outputs go to high impedance,

and the current consumption is minimized). When

RP is driven High, VIH, the device is in normal op-

eration. After exiting Reset mode, the memory en-

ters Read mode.

CPU Reset (INIT). The CPU Reset, INIT, signal

is used to Reset the device when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, FWH0/LAD0-FWH3/LAD3.

The Clock conforms to the PCI specification.

Top Block Lock (TBL). The Top Block Lock in-

put is used to prevent the Top Block (Block 7) from

being changed. When Top Block Lock, TBL, is

driven Low, VIL, program and erase operations in

the Top Block have no effect, regardless of the

state of the Lock Register. When Top Block Lock,

TBL, is driven High, VIH, the protection of the Block

is determined by the Lock Register. The state of

Top Block Lock, TBL, does not affect the protec-

tion of the Main Blocks (Blocks 0 to 6). For details,

see APPENDIX A..

Top Block Lock, TBL, must be set prior to a pro-

gram or erase operation being initiated, and must

not be changed until the operation has completed,

otherwise unpredictable results may occur. Simi-

larly, unpredictable behavior is possible if WP is

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