M50FLW040A datasheet(12/52 Pages) STMICROELECTRONICS

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M50FLW040A, M50FLW040B

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Table 5. Memory Identification Input Configuration (LPC mode)

BUS OPERATIONS

The two interfaces, A/A Mux and FWH/LPC, sup-

port similar operations, but with different bus sig-

nals and timings. The Firmware Hub/Low Pin

Count (FWH/LPC) Interface offers full functional-

ity, while the Address/Address Multiplexed (A/A

Mux) Interface is orientated for erase and program

operations.

See the sections below, The Firmware Hub/Low

Pin Count (FWH/LPC) Bus Operations and Ad-

dress/Address Multiplexed (A/A Mux) Bus Opera-

tions, for details of the bus operations on each

interface.

Firmware Hub/Low Pin Count (FWH/LPC) Bus

Operations

The M50FLW040 automatically identifies the type

of FWH/LPC protocol from the first received nibble

(START nibble) and decodes the data that it re-

ceives afterwards, according to the chosen FWH

or LPC mode. The Firmware Hub/Low Pin Count

(FWH/LPC) Interface consists of four data signals

(FWH0/LAD0-FWH3/LAD3),

one

control

line

(FWH4/LFRAME) and a clock (CLK).

Protection against accidental or malicious data

corruption is achieved using two additional signals

(TBL and WP). And two reset signals (RP and

INIT) are available to put the memory into a known

state.

The data, control and clock signals are designed

to be compatible with PCI electrical specifications.

The interface operates with clock speeds of up to

33MHz.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Bus Read. Bus Read operations are used to read

from the memory cells, specific registers in the

Command Interface or Firmware Hub/Low Pin

Count Registers. A valid Bus Read operation

starts on the rising edge of the Clock signal when

the

Input

Communication

Frame,

FWH4/

LFRAME, is Low, VIL, and the correct Start cycle

is present on FWH0/LAD0-FWH3/LAD3. On sub-

sequent clock cycles the Host will send to the

memory:

ID Select, Address and other control bits on

FWH0-FWH3 in FWH mode.

Type+Dir Address and other control bits on

LAD0-LAD3 in LPC mode.

The device responds by outputting Sync data until

the wait states have elapsed, followed by Data0-

Data3 and Data4-Data7.

See Table 6. and Table 8., and Figure 7. and Fig-

ure 9., for a description of the Field definitions for

each clock cycle of the transfer. See Table 26.,

and Figure 15., for details on the timings of the sig-

nals.

Bus Write. Bus Write operations are used to write

to the Command Interface or Firmware Hub/Low

Pin Count Registers. A valid Bus Write operation

starts on the rising edge of the Clock signal when

Input Communication Frame, FWH4/LFRAME, is

Low, VIL, and the correct Start cycle is present on

FWH0/LAD0-FWH3/LAD3. On subsequent Clock

cycles the Host will send to the memory:

ID Select, Address, other control bits, Data0-

Data3 and Data4-Data7 on FWH0-FWH3 in

FWH mode.

Cycle Type + Dir, Address, other control bits,

Data0-Data3 and Data4-Data7 on LAD0-

LAD3.

The device responds by outputting Sync data until

the wait states have elapsed.

Memory Number

ID2

ID1

ID0

A21

A20

A19

1 (Boot memory)

VIL or float

VIH

VIL or float

VIH

VIL or float

VIH

VIL or float

VIH

VIL or float

VIH

VIL or float

VIH

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