PIMXRT516SCVM2A datasheet(15/124 Pages) NXP

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Modules list

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

KPP

Keypad Port

Human Machine

Interfaces

The KPP is a 16-bit peripheral that can be used as a

keypad matrix interface or as general purpose

input/output (I/O). It supports 8 x 8 external key pad

matrix. Main features are:

• Multiple-key detection

• Long key-press detection

• Standby key-press detection

• Supports a 2-point and 3-point contact key matrix

LCDIFv2

Parallel RGB LCD

interface version 2

Multimedia

Peripherals

The LCDIFv2 is an enhanced version of LCDIF.

Main features are:

• Eight layers of alpha blending

• CRC check for configurable region on the final

display output after alpha blending

• Write-back channel to save the final output into

memory

LPI2C1

LPI2C2

LPI2C3

LPI2C4

LPI2C5

LPI2C6

Low Power

Inter-integrated Circuit

Connectivity and

Communications

The LPI2C is a low power Inter-Integrated Circuit (I2C)

module that supports an efficient interface to an I2C bus

as a master.

The I2C provides a method of communication between

a number of external devices. More detailed information,

see Section 4.9.2, LPI2C module timing parameters.

LPSPI1

LPSPI2

LPSPI3

LPSPI4

LPSPI5

LPSPI6

Low Power Serial

Peripheral Interface

Connectivity and

Communications

The LPSPI is a low power Serial Peripheral Interface

(SPI) module that support an efficient interface to an SPI

bus as a master and/or a slave.

• It can continue operating while the chip is in stop

modes, if an appropriate clock is available

• Designed for low CPU overhead, with DMA off

loading of FIFO register access

LPUART1

LPUART2

LPUART3

LPUART4

LPUART5

LPUART6

LPUART7

LPUART8

LPUART9

LPUART10

LPUART11

LPUART12

UART Interface

Connectivity

Peripherals

Each of the UART modules support the following serial

data transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 20 Mbps.

MECC64

Error Correcting Code

Memories and

Memory Controllers

MECC64 module supports Single Error Correction and

Double Error Detection (SECDED) ECC function to

provide reliability for 4 banks On-Chip RAM (OCRAM)

access. When ECC function is disabled, ECC OCRAM

can be also used to store data.

Table 3. i.MX RT1160 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

PIMXRT516SCVM2A Datasheet(PDF) 15 Page - NXP Semiconductors

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